A novel percolation model of leakage fluctuation behavior in gate-control dual-direction silicon controlled rectifier

Abstract

Gate structures are used as efficient auxiliary components to improve the electrostatic discharge (ESD) performance of traditional silicon controlled rectifiers (SCRs). However, it has not been explored how the gate geometry potentially affects leakage behaviors and ESD characteristics of SCR devices. In this paper, a novel percolation model is proposed to address this problem. The percolation model fundamentally interprets the leakage fluctuation behavior of the gate-control dual-direction silicon controlled rectifier (GC-DDSCR) under ESD events. Two key parameters breakdown charge (QBD) and tunneling current (Jg) are simulated to link the gate geometry and gate oxide quality, revealing the principle of the leakage fluctuation behavior. The leakage fluctuation behavior may cause GC-DDSCR to work in an unstable state, leading to the premature functional failure of the intrinsic SCR path. Two GC-DDSCRs with different gate sizes are fabricated under a 0.5 μm CMOS technology and characterized by a transmission line pulse (TLP) test. Experiment results show the GC-DDSCR with a larger gate size is more prone to the leakage fluctuation behavior and the premature functional failure. The percolation model is qualitatively verified and the understanding of the gate structure in ESD devices is deepened.