Transmission Line Pulsing Stress Research Articles

TLP/VFTLP investigation on eNVM 1T1R PCM in FD-SOI UTBB CMOS technology at room temperature

Intrinsic robustness against electrostatic discharge (ESD) like HBM or CDM is a major concern for the reliability and functionality in advanced CMOS FD-SOI technology and especially for non-volatile memory (eNVM). And it is well known that device characterizations are a first step of an ESD investigation. Thus, this R&D study the experimental results from 100 ns to 1 ns transmission line pulse (TLP-VFTLP) on 1T1R phase change memory (PCM) at 300 mm wafer level and at room temperature are reported here. Two types of devices are fabricated and characterized in the standard fully depleted (FD) silicon-on-insulator (SOI) with ultra-thin body and BOX (UTBB). These devices have no additional technological step and are embedded in the final memory cell topology with its selector NMOS transistor. The idea is to evaluate the behaviour of the 1T1R device under transmission line pulse stress with different stress durations. TLP/VFTLP I-V curves are reported and discussed along with post-DC responses to determine the magnitude of the phase change generated by the ESD pulse. These characterizations are important for automotive, micro-controllers, neuromorphic computing and spatial applications depending on their dedicated mission profiles at room or cryogenic temperature.

Degradation Behavior and Mechanism of SiC Power MOSFETs Under Repetitive Transmission Line Pulse Stress

The electrostatic discharge robustness of silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) are investigated by the transmission line pulse (TLP) method. The degradation behavior of key electrical parameters of the device under repetitive TLP stress is investigated. A decrease in threshold voltage, an increase in gate leakage current, and the degradation of gate capacitance parameters are observed compared with the prestress values. Low-frequency noise (LFN) test results show that after multiple TLP stress cycles, the typical leakage current noise of the device increases by approximately one order of magnitude compared to prestress, which means that the trap density extracted based on the McWhorter model increases by one order of magnitude after 1000 TLP stress pulses. Furthermore, sources of defects in the gate oxide dielectric of the devices after stresses are analyzed. The physical mechanism of the changes of SiC MOSFETs characteristics could be attributed to the hole trapping by oxygen vacancy defects and single carbon interstitial in the oxide layer after TLP stresses, which induces an electrostatic effect and results in the changes in the electrical properties of the devices. The results may be useful in the design and application of SiC power MOSFETs.

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

Gate Failure Behavior and Mechanism of AlGaN/GaN HEMTs Under Transmission Line Pulsed Stress

The failure behavior and the corresponding physical mechanism of the AlGaN/GaN high electron mobility transistors (HEMTs) under transmission line pulse (TLP) stress were investigated in this paper. The result shows that the output and transfer characteristics of the AlGaN/GaN HEMTs after 90 cycles begin to degrade by comparing with the fresh ones under 40 V TLP voltage, and the gate leakage current of the devices slightly increases. When the TLP voltage of 52 V was applied, a catastrophic failure occurs for the AlGaN/GaN HEMTs. Furthermore, the failure of the AlGaN/GaN HEMTs was located, and the micro-morphology of the abnormal spot was observed. The result shows that the gate metal was damaged due to the large TLP stress. The failure mechanism may be mainly attributed to the Joule heat that causes the high lattice temperature of 1160 K as well as the electric field, and it is higher than the melting point of Au (1064 K) in the gate metal (Au/Ti/Mo). The results may be useful in the design and application of electrostatic discharge (ESD) for AlGaN/GaN HEMTs.

Distinct Failure Modes of AlGaN/GaN HEMTs Under ESD Conditions

This article reports the distinct failure mechanisms and insights on device degradation of AlGaN/GaN high electron mobility transistors (HEMTs) under electrostatic discharge (ESD) stress conditions. The role of device surface, MESA isolation, and gate Schottky junction in defining the degradation type is discovered. Premature breakdown at the MESA Schottky junction and dislocation induced failure in the active region and their consequences on ESD robustness are reported. Physical mechanisms responsible for snapback instability in transmission line pulsing (TLP) characteristics are discussed. Change in device failure from soft to hard with pulsewidth is revealed. Finally, the role of contact resistivity, surface diffusion, and channel electric field and its fringing effect at contacts are analyzed in context to ESD failure of AlGaN/GaN HEMTs. Various stages of device degradation during TLP stress are captured on-the-fly using high-resolution (HR) optical microscopy and high-speed Si charge-coupled device (CCD) detector. Postdevice failure, damaged regions are analyzed using transmission electron microscopy and scanning electron microscopy together with in situ energy-dispersive X-ray spectroscopy to probe details of failure mechanisms involved. Finally, based on the learning from this article, design guidelines for an ESD robust HEMT are proposed.

Analysis of the role of the parasitic BJT of Super-Junction power MOSFET under TLP stress

The Super-Junction power Metal-Oxide-Semiconductor Field-Effect-Transistor (SJ-MOSFET) is one of the main switches in solar, lighting, consumer, server, and telecom applications. Among other market requirements a long lifetime is crucial, thus device robustness and reliability are decisive in quality assessment. Several failures are attributed to the action of the parasitic Bipolar Junction Transistor (BJT) inherent to the physical structure of the SJ-MOSFET. Our purpose is to gain insight into the role of the parasitic BJT under fast voltage pulse condition and to determine if the Transmission Line Pulse (TLP) can be used as a new method for predicting the Single Event Burnout (SEB) sensitivity of SJ-MOSFETs. SEB is caused by extreme localized triggering of the parasitic BJT while the whole device is in the off-state. However, TLP is uniform across a device and drives it into the avalanche multiplication regime. We demonstrate by direct comparison to equivalent SJ-Diodes that the parasitic BJT stabilizes the SJ-MOSFET when subjected to high voltage pulses generated by a TLP system. We conclude that the fast voltage method is not suited for emulating cosmic ray induced failure, but shows immense potential in analyzing device failure in other regimes.

Degradation mechanisms in gate-all-around silicon Nanowire field effect transistor under electrostatic discharge stress – a modeling approach

The failure and degradation mechanisms of gate-all-around silicon nanowire FET subjected to electrostatic discharge (ESD) are investigated through device modeling. Transmission line pulse stress test is simulated and device degradation physics is modeled. The device degradation level, interface state concentration and hard breakdown are shown and analyzed. From the model, we found that ESD stress can induce severe performance degradation or even hard breakdown of gate-all-around nanowire device, and the interface traps due to hot carrier injection is responsible for the device degradation.

Development of an Electrostatic Discharge Protection Solution in GaN Technology

In this letter, a robust and effective gallium nitride (GaN)-pHEMT-based electrostatic discharge (ESD) protection structure is developed for the first time. The structure consists of a depletion-mode GaN pHEMT, a trigger diode chain, a pinchoff diode chain, and a current limiter. Results pertinent to critical ESD parameters, such as the trigger voltage, leakage current, on-state resistance, and robustness, are measured using the transmission line pulsing (TLP) tester. It is demonstrated that such an ESD clamp can sustain a TLP stress of up to 3 A. The two diode chains are found to play critical roles in determining the trigger voltage and leakage current. Increasing the trigger diode number increases the trigger voltage. On the other hand, adding more pinchoff diodes also increases the trigger voltage and simultaneously reduces the leakage current. The design tradeoffs for the proposed ESD clamp are also discussed.

Characterization analysis of UDSM LVTSCR under TLP stress

The characteristics of a low-voltage triggering silicon-controlled rectifier (LVTSCR) under a transmission line pulse (TLP) and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge (ESD) design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron (UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.

Failure Analysis of Si Nanowire Field-Effect Transistors Subject to Electrostatic Discharge Stresses

The failure mechanisms of silicon nanowire field-effect transistors subject to electrostatic discharge (ESD) stresses are investigated using electrical characterization and microscopy analysis. Current-voltage measurements are carried out before and after the devices are stressed with ESD equivalent pulses generated from the transmission line pulsing (TLP) tester. Depending on the TLP stress level, either a soft or a hard failure can take place in the nanowire devices due to the nondestructive damage or destructive fusing of nanowires and the surrounding gate oxide.

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power transistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.

Ruggedness of Integrated VDMOS Transistors Under TLP Stress

The ruggedness of integrated vertical DMOS transistors under transmission line pulsing stress is experimentally investigated at current levels close to the thermal failure current. In addition to the parasitic vertical bipolar closest to the n-sinker contact, the lateral n-p-n transistor with the p-type junction termination as a base also goes into avalanche and supports the total current. As such, the total heat generation in the transistor is shared over a larger cross section, reducing the peak temperature. Along the device width, multiple traveling current filaments are observed; the speed of each individual filament is decreasing with the stress current. A model to predict the normalized thermal failure current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tf</sub> as a function of the device width is proposed. It is shown that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tf</sub> follows a ~W <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-0.5</sup> dependence

Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.

Internal behavior of BCD ESD protection devices under TLP and very-fast TLP stress

BCD electrostatic discharge (ESD) protection npn devices with different layout variations are analyzed experimentally and by device simulation. The device internal thermal and free carrier density distributions during the transmission line pulse (TLP) and very-fast transmission line pulse (vf-TLP) stresses are studied by a backside transient interferometric mapping technique. The lateral part of the npn transistor dominates the devices operation. The action of the vertical part of the transistor is influenced by the device layout. Experimentally observed activity of both parts of the npn transistor is well reproduced by the simulation. The devices exhibit an excellent ESD performance at both TLP and vf-TLP stress.

Microanalysis and electromigration reliability performance of high current transmission line pulse (TLP) stressed copper interconnects

Electrostatic discharge events can degrade the electromigration (EM) reliability of devices. Transmission line pulsing stress analysis is used to evaluate electrostatic discharge robustness of copper (Cu) interconnects and the impact to EM performance. Compelling evidence from transmission electron microscope data suggests the change in the microstructure of the interconnects explains the creation of latent EM failures.

Rise-time effects in grounded gate nMOS transistors under transmission line pulse stress

In this paper, the clamping voltage of a grounded gate nMOS transistor (ggnMOSt) under transmission line pulse (TLP) stress has been analysed in detail by means of a mixed-mode simulator. We show that the breakdown voltage of the ggnMOSt measured in static conditions could underestimate the maximum voltage across the protection structure obtained by TLP stress, depending on the rise time of the applied pulse. In particular, the smaller the rise time, the larger the peak reached for the drain voltage. In this paper, we will show that this can be attributed to the charging of the overlap capacitance. The influence of the LDD implant option with respect to the standard implant has also been investigated. The relationship between the maximum clamping voltage and the triggering voltage of the parasitic bipolar transistor associated with the structure is explained. A simple analytical model describing the response of the device in the early phase of the forced pulse is presented.