Transition Faults Research Articles

Reducing the input test data volume under transparent scan

Under an approach to test compaction called transparent scan, a scan circuit is considered as a sequential circuit where the scan-chain inputs and scan-select input are included in the set of inputs of the circuit. This provides the flexibility to interleave functional and scan clock cycles in arbitrary ways, and enhances the ability of transparent-scan sequences to detect target faults. These features are used in this study for reducing the input test data volume by using the same scan-chain input sequences with different scan-select sequences to define transparent-scan sequences. The circuits under consideration have a scan chain that includes their state variables, primary inputs and primary outputs. Scan-chain input sequences are computed based on a given conventional scan-based test set that includes compacted single-cycle and two-cycle test sets for single stuck-at and transition faults, respectively. The set of scan-select sequences is fixed. Using the same scan-chain input sequences for defining several transparent-scan sequences, with different scan-select sequences, allows more faults to be detected with the same set of scan-chain input sequences. This allows the number of scan-chain input sequences to be reduced compared with the number of tests in the conventional scan-based test set.

Structural Characterization of Lateral-grown 6H-SiC a/m-plane Seed Crystals by Hot Wall CVD Epitaxy

ABSTRACTThe performance of commercially available silicon carbide (SiC) power devices is limited due to inherently high density of screw dislocations (SD), which are necessary for maintaining polytype during boule growth and commercially viable growth rates. The NASA Glenn Research Center (GRC) has recently proposed a new bulk growth process based on axial fiber growth (parallel to the c-axis) followed by lateral expansion (perpendicular to the c-axis) for producing multi-faceted m-plane SiC boules that can potentially produce wafers with as few as one SD per wafer. In order to implement this novel growth technique, the lateral homoepitaxial growth expansion of a SiC fiber without introducing a significant number of additional defects is critical. Lateral expansion is being investigated by hot wall chemical vapor deposition (HWCVD) growth of 6H-SiC a/m-plane seed crystals (0.8mm x 0.5mm x 15mm) designed to replicate axially grown SiC single crystal fibers. The post-growth crystals exhibit hexagonal morphology with approximately 1500 μm (1.5 mm) of total lateral expansion. Preliminary analysis by synchrotron white beam x-ray topography (SWBXT) confirms that the growth was homoepitaxial, matching the polytype of the respective underlying region of the seed crystal. Axial and transverse sections from the as-grown crystal samples were characterized in detail by a combination of SWBXT, transmission electron microscopy (TEM) and Raman spectroscopy to map defect types and distribution. X-ray diffraction analysis indicates the seed crystal contained stacking disorders and this appears to have been reproduced in the lateral growth sections. Analysis of the relative intensity for folded transverse acoustic (FTA) and optical (FTO) modes on the Raman spectra indicate the existence of stacking faults (SFs). Further, the density of stacking faults is higher in the seed than in the grown crystal. Bundles of dislocations are observed propagating from the seed in m-axis lateral directions. Contrast extinction analysis of these dislocation lines reveals they are edge type basal plane dislocations that track the growth direction. Polytype phase transition and stacking faults were observed by high-resolution TEM (HRTEM), in agreement with SWBXT and Raman scattering.

Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults

A test set includes a significant amount of information about input assignments that prevent the faults that it does not detect from being detected. The procedure described in this paper extracts this information and uses it to guide an efficient test generation process that is fundamentally different from existing processes. Even with limited computational complexity, this new process is able to generate tests for hard-to-detect transition faults that are not detected by a test set that consists of both broadside and skewed-load tests. The basic idea is the following. Let t be a test that does not detect a fault f. The procedure extracts from t a minimal subset of values that prevent f from being detected. These values are included in a partially-specified test, which is referred to as a nontest cube. In a basic step, the procedure finds a nontest cube for f based on t. It then modifies t by complementing one specified value of the nontest cube to ensure that it does not prevent f from being detected. This is repeated until a test is found or a termination condition is reached. The nontest cubes are also used for finding necessary assignments and identifying undetectable faults.

Built-in generation of multicycle functional broadside tests with observation points

Functional broadside tests allow overtesting to be avoided as part of a scheme that considers both test generation and the analysis of output responses, by ensuring that delay faults are detected under functional operation conditions. Compared with two-cycle tests, multicycle tests allow more faults to be detected with each test, thus reducing the number of tests that need to be applied. They also provide an opportunity for nonfunctional electrical effects, which are caused by switching between modes of operation, to subside before the clock cycles where delay faults are detected. Built-in test generation facilitates at-speed testing and reduces the test data volume. Motivated by these observations, this article describes the modification of a built-in test generation method for two-cycle functional broadside tests so as to generate multicycle functional broadside tests. The size of the hardware is not increased by the modification. The article investigates the following issues related to this method: (1) the effect of using multicycle tests on the number of tests that need to be applied; (2) fault simulation for tailoring the test generation hardware to a circuit that takes into account, to different extents, the need to allow nonfunctional electrical effects to subside; (3) the insertion of observation points in order to increase the transition fault coverage.

Functional Broadside Templates for Low-Power Test Generation

This brief describes a new approach to low-power test generation targeting the maximum switching activity during the fast functional clock cycles of broadside tests. This brief defines functional broadside templates as incompletely-specified broadside tests, which capture the signal-transitions that occur during the fast functional clock cycles of functional broadside tests. The same signal-transitions can occur during functional operation. Therefore, functional broadside templates can guide the generation of low-power test sets when the goal is to match the power dissipation that is possible during functional operation on a line-by-line basis. This brief describes a procedure for computing functional broadside templates from completely-specified functional broadside tests, and a low-power test generation procedure for transition faults based on templates.

On Test Compaction of Broadside and Skewed-Load Test Cubes

For a test set that consists of test cubes (incompletely specified tests), test compaction can be achieved by merging pairs of compatible tests (tests that do not conflict in any of their specified values). This paper describes a test compaction procedure that enhances the ability of test-merging to reduce the number of tests in an incompletely specified test set that consists of both broadside and skewed-load tests for transition faults. In a basic step, the procedure attempts to remove a test t by combining it with several other tests, even if the tests are not compatible or have different types. This increases the possibility that all the faults detected by t will be detected by other tests, and t will be removed. Simulation results demonstrate reductions in numbers of tests beyond those achieved by test-merging with the same or lower numbers of specified values.

Delay fault testing using partial multiple scan chains

Delay test patterns can be generated at the functional level of the circuit using a software prototype model, when the primary inputs, the primary outputs and the state variables are available only. Functional delay test can be constructed for scan and non-scan sequential circuits. Functional delay test constructed using software prototype model can detect transition faults at the structural level quite well. Therefore, we propose a new iterative functional test generation approach. The proposed approach involves a partial multiple scan chain construction using the results of functional delay test generation at a high level of abstraction. The iterativeness of the method allows finding the compromise between the test coverage, hardware overhead and test length. Furthermore, using the partial multiple scan chains requires less hardware overhead resulting in shorter test application times. The experimental results are provided for the ITC’99 benchmark circuits. Experiments showed that the obtained transition fault coverage is on average 2% higher than using full scan and commercial automatic test pattern generator for transition faults.

Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests

The scan-in states of functional broadside tests are reachable states, which are states that the circuit can enter during functional operation. This is used for ensuring functional operation conditions during the functional clock cycles of the tests. For a partially-functional broadside test, the scan-in state has a known Hamming distance to a reachable state. This ensures measurable deviations from functional operation conditions during the functional clock cycles of the test. It is important for addressing overtesting as well as excessive power dissipation. This brief develops a fault-simulation procedure for transition faults under arbitrary (functional and nonfunctional) broadside tests that considers the tests as partially-functional broadside tests. The procedure can be used for evaluating the proximity to functional operation conditions of arbitrary broadside test sets. For illustration, the procedure is used for comparing a low-power test set with an arbitrary broadside test set.

Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes

This brief considers circuits with multiple scan chains where each scan chain can operate in shift, functional, or hold mode independently of the other scan chains. For circuits where the hardware overhead of controlling the scan chains independently is acceptable, this brief describes a procedure whose goal is to generate a test set that achieves the same transition fault coverage as a test set that consists of both broadside and skewed-load tests, but where the shift mode is used as few times as possible during the first patterns of the tests. This allows the circuit to operate closer to its functional operation conditions, and reduces the power dissipation during the second patterns of the tests, which are applied at-speed.

Seismic images of the Transition fault and the unstable Yakutat–Pacific–North American triple junction

Research Article| May 01, 2013 Seismic images of the Transition fault and the unstable Yakutat–Pacific–North American triple junction S.P.S. Gulick; S.P.S. Gulick 1Institute for Geophysics, Jackson School of Geosciences, The University of Texas at Austin, Austin, Texas 78712, USA Search for other works by this author on: GSW Google Scholar R.S. Reece; R.S. Reece 1Institute for Geophysics, Jackson School of Geosciences, The University of Texas at Austin, Austin, Texas 78712, USA Search for other works by this author on: GSW Google Scholar G.L. Christeson; G.L. Christeson 1Institute for Geophysics, Jackson School of Geosciences, The University of Texas at Austin, Austin, Texas 78712, USA Search for other works by this author on: GSW Google Scholar H. van Avendonk; H. van Avendonk 1Institute for Geophysics, Jackson School of Geosciences, The University of Texas at Austin, Austin, Texas 78712, USA Search for other works by this author on: GSW Google Scholar L.L. Worthington; L.L. Worthington 2Department of Geology and Geophysics, School of Geosciences, Texas A&M University, College Station, Texas 77843, USA Search for other works by this author on: GSW Google Scholar T.L. Pavlis T.L. Pavlis 3Department of Geological Sciences, University of Texas at El Paso, El Paso, Texas 79968, USA Search for other works by this author on: GSW Google Scholar Geology (2013) 41 (5): 571–574. https://doi.org/10.1130/G33900.1 Article history received: 30 Jul 2012 rev-recd: 21 Nov 2012 accepted: 05 Dec 2012 first online: 09 Mar 2017 Cite View This Citation Add to Citation Manager Share Icon Share Facebook Twitter LinkedIn MailTo Tools Icon Tools Get Permissions Search Site Citation S.P.S. Gulick, R.S. Reece, G.L. Christeson, H. van Avendonk, L.L. Worthington, T.L. Pavlis; Seismic images of the Transition fault and the unstable Yakutat–Pacific–North American triple junction. Geology 2013;; 41 (5): 571–574. doi: https://doi.org/10.1130/G33900.1 Download citation file: Ris (Zotero) Refmanager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu toolbar search search input Search input auto suggest filter your search All ContentBy SocietyGeology Search Advanced Search Abstract In southern Alaska, the Pacific plate and Yakutat terrane subduct beneath the North American plate along the Aleutian Trench and Pamplona zone, respectively, and are sliding past each other at minimal rates along the Transition fault. As the deformation front of the Pamplona zone stepped eastward during the Pliocene–Pleistocene, the Pacific–North American–Yakutat triple junction became unstable. Four recent seismic images reveal that the Transition fault changes from a single strike-slip boundary east of the deformation front to three strands that step increasingly seaward between the deformation front and the Aleutian Trench. The southern two strands deform the Pacific crust, and the outermost of these became increasingly convergent sometime since 1 Ma, as demonstrated by young growth strata. We propose that this internal deformation of the Pacific plate is an attempt to re-attain stability, which can only be reached by creating a tectonic boundary collinear with the Pamplona zone. The plate reorganization will result in initiation of subduction such that a portion of former Pacific crust will become accreted to the North American plate. Such accretion events caused by triple-junction instability may be an important mechanism for transferring oceanic crust to continental margins. You do not have access to this content, please speak to your institutional administrator if you feel you should have access.

The role of farfield tectonic stress in oceanic intraplate deformation, Gulf of Alaska

An integration of geophysical data from the Pacific Plate reveals plate bending anomalies, massive intraplate shearing and deformation, and a lack of oceanic crust magnetic lineaments in different regions across the Gulf of Alaska. We argue that farfield stress from the Yakutat Terrane collision with North America is the major driver for these unusual features. Similar plate motion vectors indicate that the Pacific plate and Yakutat Terrane are largely coupled along their boundary, the Transition Fault, with minimal translation. Our study shows that the Pacific Plate subduction angle shallows toward the Yakutat Terrane and supports the theory that the Pacific Plate and Yakutat Terrane maintain coupling along the subducted region of the Transition Fault. We argue that the outboard transfer of collisional stress to the Pacific Plate could have resulted in significant strain in the NE corner of the Pacific Plate, which created pathways for igneous sill formation just above the Pacific Plate crust in the Surveyor Fan. A shift in Pacific Plate motion during the late Miocene altered the Yakutat collision with North America, changing the stress transfer regime and potentially terminating associated strain in the NE corner of the Pacific Plate. The collision further intensified as the thickest portion of the Yakutat Terrane began to subduct during the Pleistocene, possibly providing the impetus for the creation of the Gulf of Alaska Shear Zone, a > 200 km zone of intraplate strike‐slip faults that extend from the Transition Fault out into the Pacific Plate. This study highlights the importance of farfield stress from complex tectonic regimes in consideration of large‐scale oceanic intraplate deformation.

Diagnostic Test Sets with Increased Switching Activity for Transition Faults

Diagnostic Test Sets with Increased Switching Activity for Transition Faults

Broadside and Skewed-Load Tests Under Primary Input Constraints

Tester limitations may impose certain constraints on the primary input vectors applicable as part of a two-pattern test for delay faults. Under these constraints, the primary input vectors may be held constant, or the second primary input vector of a test may be obtained by a single shift of a scan chain relative to the first. The goal of this brief is to study the differences in achievable transition fault coverage between various primary input constraints that are similar to the commonly used ones of holding or shifting primary input vectors. This brief also studies the possibility of combining the constraints in order to increase the transition fault coverage. The combination requires a fixed and circuit-independent hardware structure similar to the case where shifting of primary input vectors is used. This study is done using test sets that consist of both broadside and skewed-load tests in order to maximize the transition fault coverage.

An Adjacent Switching Activity Metric under Functional Broadside Tests

The local switching activity of scan-based tests is important due to the possibility that scan-based tests will result in excessive power dissipation in certain subcircuits even when the total power dissipation is acceptable. This paper focuses on the local switching activity during the fast functional capture cycles of functional broadside tests. This switching activity is guaranteed not to exceed the switching activity possible during functional operation. Therefore, with functional broadside tests it is possible to maximize the switching activity without causing excessive power dissipation. This is important for test quality since, in general, higher switching activity allows more delay defects to be detected. In addition, it allows smaller test sets to be obtained for delay faults. The paper defines a switching activity metric called the adjacent switching activity that captures the switching activity around the sites of detected transition faults, where additional switching activity is most likely to contribute to test quality. It compares the cases where the adjacent and the total switching activity of functional broadside tests for transition faults are maximized. The results demonstrate that the two objectives result in significantly different test sets. Moreover, better quality test sets are obtained by maximizing the adjacent switching activity.

Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure

Functional broadside tests are two-pattern scan-based tests that avoid overtesting by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. In addition, the power dissipation during the fast functional clock cycles of functional broadside tests does not exceed that possible during functional operation. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using a simple and fixed hardware structure, with a small number of parameters that need to be tailored to a given circuit, and can achieve high transition fault coverage for testable circuits. With the proposed on-chip test generation method, the circuit is used for generating reachable states during test application. This alleviates the need to compute reachable states offline.

Functional delay test generation approach using a software prototype of the circuit

The paper presents functional delay test generation approach for non-scan synchronous sequential circuits. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles. The software prototype model is used for the representation of the function of the circuit. The faults are considered on the inputs and on the outputs of the model only. The random input stimuli are generated and selected then according to the proposed approach. The experimental results demonstrate the superiority of the delay test stimuli generated at the functional level using the introduced approach against the transition test stimuli obtained at the gate level by deterministic test generator. The functional delay test generation approach especially is useful for the circuits, when the long test sequences are needed in order to detect transition faults.

Counter-Based Output Selection for Test Response Compaction

Output selection is a recently proposed test response compaction method, where only a subset of output response bits is selected for observation. It can achieve zero aliasing, full X-tolerance, and high diagnosability. One critical issue for output selection is how to implement the selection hardware. In this paper, we present a counter-based output selection scheme that employs only a counter and a multiplexer, hence involving very small area overhead and simple test control. The proposed scheme is ATPG-independent and thus can easily be incorporated into a typical design flow. Two efficient output selection algorithms are presented to determine the desired output responses, one using a single counter operation for simpler test control and the other using more counter operations for achieving a better test-response reduction ratio. Experimental results show that for stuck-at faults in large ISCAS'89 and ITC'99 benchmark circuits, 48%~90% reduction ratios on test responses can be achieved with only one counter and one multiplexer employed. Even better results, i.e., 76%~95% reductions, can be obtained for transition faults. It is also shown that the diagnostic resolution of this method is almost the same as that achieved by observing all output responses.

Static test compaction for mixed broadside and skewed‐load transition fault test sets

Test sets that consist of both broadside and skewed-load tests provide improved delay fault coverage for standard-scan circuits. This study describes a static test compaction procedure for such test sets. The unique feature of the procedure is that it can modify the type of a test (from broadside to skewed-load or from skewed-load to broadside) if this contributes to test compaction. Given a test set W, the basic static test compaction procedure described in this study considers for inclusion in the compacted test set both a broadside and a skewed-load test based on every test w ∈ W. It selects the test type that detects the higher number of faults. An improved procedure considers a broadside and a skewed-load test based on a test w ∈ W only if w detects a minimum number of faults (without changing its type). Experimental results demonstrate that the static test compaction procedure is typically able to reduce the sizes of mixed test sets further than a procedure that does not modify test types. The procedure modifies the types of significant numbers of tests before including them in the compacted test set.

A Metric for Identifying Detectable Path Delay Faults

Path delay faults are used for modeling small delay defects. Due to the large numbers of paths and the large numbers of undetectable path delay faults, test generation procedures for path delay faults use path selection procedures and procedures for the identification of undetectable faults to facilitate test generation. To complement these procedures, this paper describes a metric for assessing the likelihood that a path delay fault is detectable. Path selection procedures should prefer such faults in order to yield sets of target faults that are detectable even if not all the undetectable faults are identified prior to test generation. The metric is defined such that it allows all the path delay faults with the same value of the metric (the same likelihood of being detectable) to be enumerated together. The metric is computed based on the numbers of detections of transition faults under a test set for such faults, and requires N-detection fault simulation of transition faults for a sufficiently large value of N. The results of test generation for path delay faults confirm that faults with higher values of the metric are more likely to be detectable.

Tremor asperities in the transition zone control evolution of slow earthquakes

Slow earthquakes, characterized by slow slip and associated seismic radiation called non‐volcanic tremor, have been observed in major subduction zones worldwide. They constitute an important mode of stress release for the fault's transition zone, which lies directly downdip of the locked segment, the nucleation zone of large damaging earthquakes. However, the depth of tremor in Cascadia, and the factors governing tremor generation and rupture propagation during slow quakes remain enigmatic. Here, we develop a novel multibeam‐backprojection (MBBP) method to detect and locate tremor using multiple mini seismic arrays. We apply this technique to image tremor activity during an entire ETS‐cycle including a large episodic tremor and slip (ETS) event in Cascadia with unprecedented resolution. Our results suggest that the majority of the tremor is occurring near the plate interface. We observe strongly heterogeneous tremor distribution with patches in the transition zone that experience repeated tremor episodes and produce most of the tremor. The patches, tens of kilometers in dimension, behave like asperities on the fault plane. During the large ETS event, rupture propagation velocity varies at least by a factor of five, and seems to be modulated by these tremor asperities. These observations support a model in which the transition zone is heterogeneous and consists of patches of asperities with surrounding regions slipping aseismically. The asperities fail quasi‐periodically releasing stress and appear to regulate rupture propagation and tremor generation during slow earthquakes. This study presents new observations revealing the tectonic characteristics of the transition zone controlling the generation and evolution of slow earthquakes.