Transfer Characteristics Of Transistors Research Articles

Dimensional Effect on DIBL in Silicon Nanowire Transistors

Drain-induced barrier lowering (DIBL) is crucial in many applications of silicon nanowire transistors. This paper determined the effect of the dimensions of nanowires on DIBL. The MuGFET simulation tool was used to investigate the characteristics of the transistors. The transfer characteristics of transistors with different dimensions were simulated. The results show that longer nanowires with smaller diameters and lower oxide thickness decrease DIBL and tend to possess the best transistor characteristics.

Spray-coated carbon nanotube thin-film transistors with striped transport channels

We present results for the transfer characteristics of carbon nanotube thin-film transistors (CNT-TFTs) that utilize single-walled carbon nanotube thin-films prepared by direct spray-coating on the substrate. By varying the number of spray-coatings (Nsp) and the concentration of nanotubes in solution (CNT), it was possible to control the conductivity of the spray-coated nanotube thin-film from 129 to 0.1 kΩ/□. Also, by introducing stripes into the channel of the CNT-TFT, and thereby reducing the number of metallic percolation paths between source and drain, it was possible to enhance the on/off current ratio 1000-fold, from 10 to 104, demonstrating that it may be possible to utilize spray-coating as a method to fabricate CNT-TFTs for large area switching array applications.

Improvement in the I–V characteristics of carbon nanotube network transistors using microwave treatment

This work describes the effects of microwave irradiation on the transfer characteristics of single-walled carbon-nanotube network transistors. The microwave treatment dramatically increases the on-off ratio of the electrical currents by reducing the off-state current. Detailed analyses of Raman spectroscopy data, the thermal effect, and a direct image comparison suggest preferential removal of the metallic paths formed in the transistor channel. This treatment can be utilized as method to repair for electrically failed transistors even after completion of device fabrication.

Effect of interface charge on the dc bias stress-induced deformation and shift of the transfer characteristic of amorphous oxide thin-film transistors

The presence of a deformation or hump in the subthreshold region of the transfer characteristic of Amorphous Oxide Semiconductor (AOS) Thin-Film Transistors (TFTs) has been observed after DC stress and related to different causes. In previous works, it has been shown that in devices with active-layer thickness greater than 120nm, a region with relatively high conductivity remains near the back interface of the active layer, providing a parallel current path between drain and source giving rise to this deformation. If this is the cause of the hump, it should be present independently of bias stress. However, experiments show that the hump is observed in AOS TFTs with active layer thickness below 120nm and only after DC stress. In this work we show that, if during DC bias stress, the density of positively charged states at the interface between the active layer and the passivation layer of an AOS TFT becomes high enough to provide a parallel conduction path, the deformation or hump in the transfer curve can appear. This condition is more likely to occur in devices passivated with dielectrics that can present charged traps at the dielectric–semiconductor interface and agrees well with experimental data reported for AOS TFTs.

Effects of dry oxidation of heavily doped p-type Si on output and transfer characteristics in organic thin film transistors

► A SiO 2 layer was grown on the heavily doped p-type Si using a dry oxidation process. ► The effect of an O 2 gas flow on the quality of thermally growing SiO 2 was examined. ► A low O 2 gas flow led to the formation of the intermediate oxygen deficient oxide. ► The significant gate leakage is the major source of the drain offset. This paper presents an analysis of the effect of the SiO 2 /Si interfacial property on output (transfer) characteristics of organic thin film transistors (OTFTs). A SiO 2 layer was grown on the heavily doped p-type Si wafer using a dry oxidation process as a gate oxide layer. The electrical conduction investigations suggest that the leakage behavior is governed by the poor insulation of the oxygen deficient oxide between SiO 2 and Si. From the observed result, the relationship between gate leakage and output (transfer) characteristics of OTFTs was discussed.

Accurate description of charge transport in organic field effect transistors using an experimentally extracted density of states

The width and shape of the density of states (DOS) are key parameters to describe the charge transport of organic semiconductors. Here we extract the DOS using scanning Kelvin probe microscopy on a self-assembled monolayer field effect transistor (SAMFET). The semiconductor is only a single monolayer which has allowed extraction of the DOS over a wide energy range, pushing the methodology to its fundamental limit. The measured DOS consists of an exponential distribution of deep states with additional localized states on top. The charge transport has been calculated in a generic variable range-hopping model that allows any DOS as input. We show that with the experimentally extracted DOS an excellent agreement between measured and calculated transfer curves is obtained. This shows that detailed knowledge of the density of states is a prerequisite to consistently describe the transfer characteristics of organic field effect transistors.

An Electrochemical Transducer Based on a Pentacene Double‐Gate Thin‐Film Transistor

AbstractWe report an electrochemical transducer based on an organic double‐gate transistor. The bottom‐gate is given by a p‐doped silicon substrate, which is covered by 300 nm thermal oxide. A 20 nm pentacene film acts as the semiconducting layer, and a 50 nm tetratetracontane (TTC) alkane film is used as a top‐gate dielectric. An aqueous ionic solution acts as top‐gate. We record the transistor transfer characteristics by variation of the electrolyte potential via a Ag/AgCl electrode for various bottom‐gate settings. A change of the electrolyte potential results in a change of the transistor current and the characteristic behaviour of the device is in good agreement with the expected behaviour of a double‐gate transistor. The top‐gate capacitance of the alkane layer is as high as 2.6×10−8 F cm−2 determined by impedance measurements, indicating that TTC is a good choice as an organic top‐gate dielectric. The suitability of this transducer configuration for sensing in aqueous media is demonstrated by the detection of hexanoic acid and stearic acid molecules adsorbing to the alkane interface, respectively. We show that the transducer easily achieves a concentration sensitivity in the range of 100 nM.

Low‐Temperature, Solution‐Processed and Alkali Metal Doped ZnO for High‐Performance Thin‐Film Transistors

Transfer characteristics of ZnO thin-film transistors (TFTs) based on ZnO doped with various alkali metals. A new doping method is demonstrated by employing alkali metals to achieve high-performance and solution-processed ZnO TFTs with a low processing temperature (∼300 °C), which is applicable to flexible plastic substrates.

Influence of Gate Corrugations on the Performance of Thin-Film Transistors

This letter investigates the influence of a corrugated gate on the transfer characteristics of thin-film transistors. Corrugations that run parallel to the length of the channel from source to drain are patterned on the gate. The author finds that these corrugations result in higher currents as compared to conventional planar-gate transistors.

Decrease of the OFF State Current of Carbon Nanotube Field Effect Transistors via Continuous Repeated Gate Sweeping

Continuous repeated gate sweeping incorporated with substrate etching step is utilized to decrease the OFF state current in single-walled carbon nanotube field effect transistors with bundled carbon nanotubes. In particular, the effects of continuous repeated gate sweeping on transfer characteristic of transistors are examined. The etching step creates suspension in transistors at contact with metal electrodes as well as causing some single-walled carbon nanotubes to dramatically burn off by electrical current. By repeating gate sweeping, source-drain current gets smaller and smaller. This will eventually lead to the OFF state current less than 2 nA. Defects in the lattice of single-walled carbon nanotubes introduced by multiple gate sweeping could be the reason for this phenomenon. Contribution from possible hole trapping is also considered.

Gas Sensing Mechanism of Gold Nanoparticles Decorated Single‐Walled Carbon Nanotubes

AbstractMetal nanoparticles decorated single‐walled carbon nanotubes (SWNTs) can lead to considerable enhancement in sensing performance towards different gas analytes, however the sensing mechanism was not clearly elucidated. The detailed sensing mechanism of hybrid gold‐SWNT nanostructures toward hydrogen sulfide was investigated using field effect transistor (FET) transfer characteristics. At low H2S concentrations (≤100 ppbV), FET transfer characteristics show that the gold nanoparticles at the surface of SWNTs acted as nano‐Schottky barriers to predominately modulate transconductance upon exposure to unfunctionalized SWNTs on gold electrodes which showed little or no response upon exposure. Although the sensitivity of Au/SWNT toward H2S was strongly dependent upon the size and number of gold nanoparticles, the sensing mechanism was independent of it.

Effect of the induced electron traps by oxygen plasma treatment on transfer characteristics of organic thin film transistors

The effect of the induced electron traps by oxygen plasma treatment on transfer characteristics of organic thin film transistors (OTFTs) was researched in this study. From the observed result, the relationship between electron trapping and electrical stability of OTFTs was discussed. It is shown that oxygen plasma treatment may lead to a shift of the threshold voltage towards positive gate-source voltages and an increase in the mobility, resulting from the incorporation of oxygen and the passivation of the defects in the grain-boundary region. It is found that the electrical stability mainly arises from the increased long-lifetime electron-trap density.

Modeling of the Output and Transfer Characteristics of Graphene Field-Effect Transistors

We obtain the output and transfer characteristics of graphene field-effect transistors by using the charge-control model for the current, based on the solution of the Boltzmann equation in the field-dependent relaxation time approximation. Closed expressions for the conductance, transconductance, and saturation voltage are derived. We found good agreement with the experimental data of Meric et al. [Nat. Nanotechnol. vol. 3, p. 684, 2008] without assuming carrier density-dependent velocity saturation.

Graphene Transistors Are Insensitive to pH Changes in Solution

We observe very small gate-voltage shifts in the transfer characteristic of as-prepared graphene field-effect transistors (GFETs) when the pH of the buffer is changed. This observation is in strong contrast to Si-based ion-sensitive FETs. The low gate-shift of a GFET can be further reduced if the graphene surface is covered with a hydrophobic fluorobenzene layer. If a thin Al-oxide layer is applied instead, the opposite happens. This suggests that clean graphene does not sense the chemical potential of protons. A GFET can therefore be used as a reference electrode in an aqueous electrolyte. Our finding sheds light on the large variety of pH-induced gate shifts that have been published for GFETs in the recent literature.

Empirical Modeling of Metal-Contact Effects on Graphene Field-Effect Transistors

An empirical model is developed to characterize metal-contact effects on the transfer characteristics of graphene field-effect transistors. The present model is based on a diffusive transport, and considers charge carrier doping from metallic electrodes to the adjacent graphene channel. An electron–hole conductivity asymmetry, one of the main features in the transfer characteristics, is well reproduced by the model. Model calculations with varied parameters show that the conductivity asymmetry becomes more distinct with higher charge-carrier mobility, higher doping level at the metal contacts, larger extent of the doped region near the contacts, or shorter channel lengths.

Charge transfer and partial pinning at the contacts as the origin of a double dip in thetransfer characteristics of graphene-based field-effect transistors

We discuss the origin of an additional dip other than the charge neutrality point observedin the transfer characteristics of graphene-based field-effect transistors with aSi/SiO2 substrate used as the back-gate. The double dip is proved to arise from chargetransfer between the graphene and the metal electrodes, while charge storage at thegraphene/SiO2 interface can make it more evident. Considering a different Fermi energy from theneutrality point along the channel and partial charge pinning at the contacts, we propose amodel which explains all the features observed in the gate voltage loops. We finally showthat the double dip enhanced hysteresis in the transfer characteristics can be exploited torealize graphene-based memory devices.

Temperature dependent transfer characteristics of graphene field effect transistors fabricated using photolithography

We report on the temperature dependent transport characteristics of graphene field effect transistors (G-FETs) fabricated using photolithographic technique. Monolayer graphene layers were selected for the fabrication of electronic devices and the fabricated devices were further annealed in Ar/H 2 at 200 °C. The temperature dependence of resistance of the graphene flake shows semiconductor-type behavior. The resistance increases about one order of magnitude upon cooling from 300 K to 8 K. Our observations are good in agreement with the previously reported temperature behavior of monolayer graphene nanoribbons and reduced graphene oxide. A higher drain-current modulation in negative back-gate field with current minimum (the Dirac point) is observed at V GS ∼ −2.75 V. The carrier mobilities were determined from the measured transconductance and obtained mobilities are less than the conductivity and mobility of pristine graphene. The reason could be discussed in detail with variable range hopping mechanism which is consistent to our resistance/temperature data.

Electrodeposited Single Crystalline PbTe Nanowires and Their Transport Properties

Single crystalline PbTe nanowires were potentiostatically electrodeposited by a template-directed method using track-etched polycarbonate membranes as scaffolds in acidic nitrate baths. They exhibited a face-centered cubic (FCC) structure with a preferred growth direction about 31° against the [200] direction. By galvanic displacing the ends of PbTe nanowire with gold prior to electrode microfabrication, the Schottky barrier (i.e., native PbTe oxide) at the interfaces between nanowire and electrodes was eliminated/reduced to form an ohmic contact between nanowire and electrodes. Field effect transistor (FET) transfer characteristics indicated that the electrodeposited single-crystalline PbTe nanowires are p-type semiconductors with the estimated field effect carrier mobility and concentration of 3.32 ± 0.15 cm2/(V s) and 1.85 ± 1.06 × 1018 cm−3, respectively.

Discrepancy in mobility extracted from transfer and output characteristics of organic thin film transistors

The discrepancy in mobility extracted from transfer and output characteristics of organic thin film transistors was studied. The extraction from transfer characteristics demonstrates higher mobility, compared to the extraction from output characteristics. It is shown that the contribution of capacitance variation may lead to an increased drain current, thus overestimating mobility.

Investigation of high frequency performance limit of graphene field effect transistors

Extremely high field effect mobility together with the high surface coverage makes graphene a promising material for high frequency electronics application. We investigate the intrinsic high frequency performance limit of graphene field effect transistors limited by the charge impurity scattering. The output and transfer characteristics of graphene field effect transistors together with the high frequency performance are characterized as a function of impurity concentration and dielectric constant of the gate insulator. Our results reveal that graphene transistors could provide power gain at radio frequency band.