Transistor Static Random Access Memory Research Articles

Comprehensive Study of Low-Power SRAM Design Topologies

Abstract: The need for low power in portable and smart devices is the demand to be fulfilled for sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main part of the core design in chips. It is important to reduce the leakage power consumption during the steady mode of the device for the long run of the battery. This article is about the study of different modules using pre-existing low power. Application of different methods other than lowering the supply voltage leads to an increment in the number of transistors in conventional 6T (six transistor) SRAM cells like 7T to 14T. Power gating and the Multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is the most relevant method. Hybrid low power techniques are in high demand because it shows better results than using individual techniques. However, the biggest challenge is to maintain the area and delay as well. FinFET came into the scenario to overcome the leakage power and short channel effect due to scaling in CMOS. Comparative study analysis shows that FinFET decreases the overall power and delay even when the number of transistors increases. A comparison was done between 6T, 8T, and 10T using FinFET and CMOS in a paper, and concluded that FinFET shows 77.792% improved write power.

A novel CNTFET based Schmitt-Trigger read decoupled 12T SRAM cell with high speed, low power, and high [formula omitted]/[formula omitted] ratio

Many researchers are working to develop a static random access memory (SRAM) cell that uses low power, has good stability, better Ion/Ioff ratio and speed. This paper presents a single sided Schmitt-trigger driven read decoupled 12 transistors (STRD 12T) carbon nanotube field-effect transistor (CNTFET) SRAM cell with controlled power gating approach. The Schmitt-trigger (ST) inverter along with power gating and read decouple approach has low power, good read and write delay, better stability and Ion/Ioff ratio. The stacking effect reduces the leakage power of the proposed cell. The proposed STRD 12T SRAM illustrates the maximum reduction in static power consumption, write delay, read delay, and maximum improvement in Ion/Ioff ratio is 1544.34, 112.37, 1.40, and 8107.88 times respectively, than the considered SRAM cells. The simulation is performed with Cadence Virtuoso utilizing the 32 nm CNTFET model from Stanford University.

Cache Memory Design for Single Bit Architecture with Different Sense燗mplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

This paper provides an overview of blockchain technology’s security and privacy features, as well as an overview of IoT-based cache memory and single-bit six transistor static random-access memory cell sense amplifier architecture. Each chip’s memory is used for recorded as blocks, which are encrypted and used as a blockchain for other memory devices. The architectures comprise of the circuit of write driver, six transistor static random access memory cells, and sense amplifiers such as current differential sense amplifier, charge transfer differential sense amplifier, and voltage latch sense amplifier. Furthermore, different parameters such as the number of transistors, sensing delay, and power consumption have been analyzed for varying resistance values (i.e., R= <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42.3\Omega $ </tex-math></inline-formula> and R=42.3K <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega$ </tex-math></inline-formula> ). Apart from that, power reduction techniques such as dual sleep, forced stack, sleep transistor, and sleep stack are used to optimize power consumption. These power reduction techniques are applied over different blocks of architecture, such as six transistors static random access memory cell and sense amplifier to optimize power consumption of the architecture. The conclusion arises that a single-bit six transistor static random access memory cell with power reduction dual sleep technique voltage latch sense amplifier with power reduction dual sleep technique in architecture consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.65~\mu \text{W}$ </tex-math></inline-formula> of power and has 33 transistors which are lowest from other architectures.

Design of low power, variation tolerant single bitline 9T SRAM cell in 16-nm technology in subthreshold region

The major design parameters of embedded cache memory (SRAM memory cell) are speed, power consumption, noise tolerance, and reliability. It is a challenging task to design an SRAM cell in the face of process, voltage, and temperature variations at low supply voltages. At scaled technology node the conventional 6T SRAM cell suffers from read and write failures as well as instability. Moreover, it is susceptible to multibit soft error rate since it does not support bit-interleaving architecture. This paper proposes a low-power robust single bitline 9T (nine transistor) SRAM (Static Random Access Memory) at a 16-nm technology node in the subthreshold region. The potency of the proposed cell is shown by comparing it with other recently published SRAM cells, namely, single-ended NTV 9T (SENTV9T), write and read enhanced 9T (WREN9T), and the conventional 6T (CONV6T) SRAM cells. The proposed cell provides 1.25×/1.96 × lower read current IREAD variability compared with WREN9T/SENTV9T. The proposed cell achieves 4.23 × higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with CONV6T due to the fact that it employs read decoupled operation. Moreover, SBL9T consumes lower standby power during hold state and dynamic power in the active state as compared with SENTV9T, WREN9T, and CONV6T. SBL9T also exhibits 10.01×/8.65×/11.47× narrower spread in standby power compared with CONV6T/WREN9T/SENTV9T. The dynamic power spread shows a similar trend with SBL9T providing 1.97×/1.02× narrower spread in dynamic power compared with WREN9T/SENTV9T. These benefits however are achieved by the SBL9T at the cost of 1.28×/0.71×/1.01× longer read delay compared with CONV6T/WREN9T/SENTV9T.

Design of a Bit-Interleaved Low Power 10T SRAM Cell with Enhanced Stability

The technology is shrinking in recent days which leads to growing concerns related to various design metrics. Leakage power tends to grow with the array size as most of the Static Random Access Memory (SRAM) cells operate in standby mode. The data to be written into the SRAM become difficult as the supply voltage decreases. So, stability in write mode requires enhancement. As SRAM is used for the on-chip computations, the faster write operation is required. The half-select issue in SRAM design needs to be eliminated so that bit interleaving architecture can be employed for the SRAM array enabling the protection from soft errors. A new Proposed 10 Transistor Bit-Interleaved SRAM cell has been designed addressing the above concerns. Employment of high-threshold voltage devices in read path and absence of NMOS device in one of the inverters reduces leakage power. Cut-off switch enables faster write operation and enhanced write stability. Cross point selection in write mode eliminates the half-select issue observed by carrying 1000 Monte-Carlo simulations. It has lower leakage power while holding 0 compared to 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at the worst fast-fast process corner for 0.9 V supply voltage. Write 1 Power Delay Product is lower than 8 Transistor, Fully Differential 8 Transistor and Write Assist Low Power 11 Transistor SRAM cells at slow-slow corner at 0.9V supply voltage. All the design metrics have been evaluated by performing post-layout simulation in Cadence Virtuoso in 45-nm technology.

Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells

We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling 6144 p- and n-type CNFETs), with all 1024 cells functioning correctly without any per-unit customization. Moreover, we show the first demonstration of CNFET CMOS 10T SRAM cells, capable of operating at highly scaled voltages down to 300 mV. We characterize the CNFET CMOS SRAM and demonstrate robust operation by writing and reading multiple patterns (to both the kbit arrays as well as the 10T SRAM cells), measuring SRAM variations in read, write, and hold margins and repeat cycling of cells. Moreover, due to the low-temperature back-end-of-line (BEOL)-compatible CNT-specific processing, CNFET SRAM enables new opportunities for digital systems, since: 1) CNFET SRAM can be fabricated directly on top of computing logic to realize three-dimensional integrated circuits; and 2) CNFET circuits can utilize metal routing both above and below the CNFET device layer (e.g., as in our demonstration which utilizes buried power rails, whereby the power rails are fabricated underneath the FETs while metal routing is fabricated above the FETs), providing opportunities for further SRAM density scaling.

Design of low leakage process tolerant SRAM cell

In this paper, a novel 8 Transistor Static Random Access Memory (SRAM) cell is proposed to reduce the static power introduced by sub threshold and gate leakages, thus reducing the total power dissipation. The power dissipation of the proposed cell in standby mode has reduced considerably, compared to the conventional 6 Transistor SRAM cell and NC SRAM cell. A better stability is achieved in this cell under different process corners. The proposed technique reduces the standby power to 6.22 nW, which is almost negligible compared to that of a 6T SRAM cell (4.23 uW). Hence, the proposed cell is more suitable for standby mode operation. The total power of the proposed cell is reduced by 25.6% and the read-stability is increased by 40% compared to the conventional 6T SRAM cell. Cadence (Virtuoso) tools are used for simulation with gpdk 45-nm process technology.

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

ANALYSIS OF STATIC NOISE MARGIN FOR NOVEL POWER GATED SRAM

Data stability is one of the important parameter of SRAM with scaling of CMOS technology. However the move to nanometer technology not only nodes has increased, but the variability in device characteristics has also increased due to large process variations. Static random access memory (SRAM) is a popular component which is used in modern microprocessors and occupies a considerable chip area. It is useful to store the data as well as read and write operation. The performance of SRAM circuit is measured with data stability and read-write SNM (Static Noise Margin). A novel power gated SRAM cell is presented in this paper with enhanced data stability and reduced leakage power. The data becomes completely isolated form bit line during read operation in new power gated SRAM. The SNM of the new power gated cell is thereby increased by 2 times in comparison to a conventional six transistor (6T) SRAM cell. The paper also covers the comparative analysis and simulation of both SRAM cell on the basis of Read Noise Margin and Write Noise Margin. The novel power gated SRAM cell has larger read and write SNM as compared to conventional 6T SRAM cell at different technologies. All results are carried out on 45nm, 32nm and 22nm CMOS technology using HSPICE simulation tool.

Leakage Analysis of a Low Power 10 Transistor SRAM Cell in 90 nm Technology

In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.

High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array

The huge area overhead of the interconnect is one of the critical issues in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), resulting in high power consumption and slow operation speed. Another critical issue is the volatile feature of the SRAM, which leads to high standby leakage current and long power-ON time. Resistive random access memory (RRAM) with a high resistance ratio and zero standby power possesses great potential in the FPGA applications. The conventional RRAM-based nonvolatile FPGAs (NVFPGAs) may use one-transistor 2-RRAM (1T2R) storage element to replace the SRAM or the one RRAM (1R) cell to replace both nMOS switch and SRAM. However, those NVFPGA schemes may suffer from the issues of low reliability, high configuration power, and high active leakage power. In this paper, we propose a novel element [one-diode two-RRAM (1D2R) cells] to replace the nMOS switch and 6 Transistors (6T) SRAM. Meanwhile, the novel block structures of the logic block, connection block, switch block, and the FPGA architecture based on the 1D2R element are proposed. Compared with the conventional 1T2R-based NVFPGA, our novel structure could improve the operation speed by 53% with a 40.5% lower operation power. Compared with the conventional 1R-based NVFPGA, the proposed scheme could greatly reduce the write error rate by eight orders with more than 20 times lower write power.

A design of low swing and multi threshold voltage based low power 12T SRAM cell

This paper focuses on the design of a novel low power twelve transistor static random access memory (12T SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines, respectively. Reduction in swing voltage reduces the dynamic power dissipation when the SRAM cell is in working mode. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep to active (OFF to ON condition) and active to sleep (ON to OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Simulation has been done in 45nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.

Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications

In this work we explore several doping schemes for aggressively scaled multi-gate field-effect transistor devices with the conduction channels wrapped around silicon fins (FinFETs) (HFin∼37 nm, WFin≥10 nm, Lg≥30 nm), using conventional ion implantation (I/I), and suitable for both logic and dense circuit applications. We demonstrate that low-energy and: 1) low-tilt, double-sided extension(-less) I/I, or 2) high-tilt, single-sided extension I/I schemes can enable pitch scaling without resist shadowing effects, with no penalty in device performance and yielding higher six transistors-static random access memory (6T-SRAM) static noise margin (SNM) values. Key advantages of the extension-less approach are: reduced cost and cycle time with 2 less critical I/I photos, enabling better quality, defect-free growth of Si-epitaxial raised source/drain (SEG), and up to 20× lower IOFF. It, however, requires a tight spacer critical dimension (CD) control, a less critical parameter for the single-sided I/I scheme, which also allows wider overlay margins.

Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach

This paper investigates the cell stability of recently introduced four-transistor (4T) and conventional six-transistor (6T) fin-shaped field-effect transistor static random access memory (SRAM) cells operating in a subthreshold region using an efficient model-based approach to consider the impact of device variations. Compared with the 6T cell, this paper indicates that 4T SRAM cells exhibit a better nominal READ static noise margin (RSNM) because of the reduced READ disturb. For 4T cells, the nearly ideal values of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">write,0</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">wriet,1</sub> guarantee the positive nominal WRITE static noise margin (WSNM) for selected cells. For half-selected cells on the selected bit line, a sufficient margin is observed between WRITE time (for selected cells) and WRITE disturb (for half-selected cells). Using the established model-based approach, the variability of subthreshold 6T and 4T SRAM cells is assessed with 1000 samples. Our results indicate that the 4T driverless cell with a larger μRSNM and a slightly worse σ-RSNM shows a comparable μ/σ ratio in RSNM with the 6T cell. Further more, for a given cell area, 4T SRAM cells using relaxed device dimensions with reduced σ-RSNM can outperform the 6T cell. For WRITE operation, 4T SRAM cells exhibit a superior WSNM, whereas the design margin between WRITE time and WRITE disturb needs to be carefully examined to ensure an adequate margin considering device variability.

DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM

This paper presents a novel design flow and algorithms for simultaneous power-stability optimization of nano-CMOS static random access memory (SRAM) circuits. A 45 nm single-ended seven transistor SRAM has been used as case study. The SRAM cell is subjected to a dual-V Th assignment based on a novel combined Design of Experiments and Integer Linear Programming (DOE-ILP) approach, resulting in 50.6% power reduction (including leakage) and 43.9% increase in the read static noise margin over the baseline design. The process variation analysis of the optimized cell is performed considering the variability effect in twelve device parameters. An 8 x 8 array is constructed to show the feasibility of the proposed SRAM cell. To the best of the authors' knowledge, this is the first research reporting the use of DOE and ILP for optimization of conflicting targets of power and stability in SRAM.

High Speed Six-Transistor Static Random Access Memory Cells Using Single Grain Thin Film Transistors Fabricated at Low Temperature Process

In this paper we will report successfully fabricated six transistor static random access memory (6T SRAM) cells using single-grain thin film transistors (TFTs). SRAM cells have been designed by analytical calculations and verified by DC and transient simulations. TFTs are fabricated by µ-Czochralski process that consists of making grain filter and Excimer laser crystallization at temperatures below 550 °C. The gate length of transistors are 2 µm. Fabricated SRAM cells based on single grain TFTs, show good read and write static noise margin (SNM and WNM) equal to 0.55 and 0.75 V at 3.3 V power supply, respectively. Finally, excellent read and write access times equal to 13 and 8 ns in 87 MHz worldline frequency were obtained.

A Low Power SRAM Cell with High Read Stability

In this paper, a 9T static random access memory (SRAM) cell design which consumes less dynamic power and has high read stability is proposed. In conventional six transistor (6T) SRAM cell, read stability is very low due to the voltage division between the access and driver transistors during read operation. Existing 9T SRAM cell design increases the read static noise margin (SNM) by twice as compared to conventional 6T SRAM cell by completely isolating the bit-lines during the read operation. But the write operation is performed in this cell, by charging/discharging of large bit line capacitances causing 22.5% increase in dynamic power consumption. In the proposed technique, the SRAM cell utilizes charging/discharging of a single bit-line (BL) during write operation, resulting in reduction of dynamic power consumption by 45% as compared to a conventional 6T SRAM cell while the read SNM is also maintained at twice the read SNM of the conventional 6T SRAM cell. All simulations of the proposed 9T SRAM cellhas been carried out in 0.13 ¹m CMOS technology.

Mitigation of Complementary Metal–Oxide–Semiconductor Variability with Metal Gate Metal–Oxide–Semiconductor Field-Effect Transistors

Variability due to Fermi level pinning at polycrystalline silicon gate grain boundary is examined as an additional source of intrinsic parameter fluctuation. Threshold voltage (Vt) variation with metal gate to avoid the variation is found to be mitigated with the measurement of n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) with an identical process except gate stack. The statistical variation of intrinsic gate delay and static noise margin of the 6 transistors static random access memory (SRAM) cell is predicted for future technology nodes using Monte Carlo circuit simulation with a process/physics-based compact model. It is found that the variability can be suppressed by ∼35% with adopting metal gate for 32 nm technology node.