Design of low leakage process tolerant SRAM cell

Abstract

In this paper, a novel 8 Transistor Static Random Access Memory (SRAM) cell is proposed to reduce the static power introduced by sub threshold and gate leakages, thus reducing the total power dissipation. The power dissipation of the proposed cell in standby mode has reduced considerably, compared to the conventional 6 Transistor SRAM cell and NC SRAM cell. A better stability is achieved in this cell under different process corners. The proposed technique reduces the standby power to 6.22 nW, which is almost negligible compared to that of a 6T SRAM cell (4.23 uW). Hence, the proposed cell is more suitable for standby mode operation. The total power of the proposed cell is reduced by 25.6% and the read-stability is increased by 40% compared to the conventional 6T SRAM cell. Cadence (Virtuoso) tools are used for simulation with gpdk 45-nm process technology.