Abstract
In this paper, a novel 10 Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write bit lines are decoupled in the proposed cell. Feedback loop-cutting with single bit line write scheme is employed in the 10 Transistor SRAM cell to reduce active power consumption during the write operation. Read access time and write access time are measured for proposed cell architecture based on Eldo SPICE simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor (CMOS) technology at various process corners. Leakage current measurements made on hold mode of operation show that proposed cell architecture is having 12.31 nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor cell. 10 Transistor cell also has better performance in terms of leakage power as compared to 6 Transistor cell.
Highlights
Static Random Access Memory (SRAM) is a vastly used circuit in modern integrated chips
This paper investigates leakage power consumption and leakage current comparison at 90 nm technology node
The analysis shows that the proposed 10 Transistor (10T) SRAM cell outperforms standard 6 Transistor (6T) SRAM cell with respect to most of its design metrics
Summary
Static Random Access Memory (SRAM) is a vastly used circuit in modern integrated chips. (2016) Leakage Analysis of a Low Power 10 Transistor SRAM Cell in 90 nm Technology. Due to scaling of device dimensions, random variations in Process, Supply Voltage and Temperature (PVT) poses major challenges to the high performance circuits and system design [1]-[3]. The static (leakage) power consumption of CMOS devices has created undesirable effects on technology scaling as both supply voltage (VDD) and threshold voltage (Vth) are scaled [1]. This paper investigates leakage power consumption and leakage current comparison at 90 nm technology node. It presents an analysis of read access time, write access time due to the impact of process corners at different supply voltages. The analysis shows that the proposed 10T SRAM cell outperforms standard 6T SRAM cell with respect to most of its design metrics
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have