Transistor Stacking Research Articles

1V 2GHz CMOS frequency divider

A new frequency divider, called differential injection locking, is proposed. The proposed divider has no transistor stacking to suppress the performance degradation due to supply voltage reduction. It is shown that the proposed frequency divider achieves 2 GHz with 1 V supply voltage and 540 µW power consumption.

Gate leakage reduction for scaled devices using transistor stacking

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L/sub eff/) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.

Source-injection parallel coupled LC-QVCO

A simple source-injection parallel-coupled (SIPC) LC quadrature voltage controlled oscillator (QVCO) in which the additional noise contributions of the coupling transistors are nearly zero is proposed. The proposed topology is suitable for low phase noise and low supply voltage operation since it involves no additional transistor stacking. Compared to the conventional LC-QVCO, the SIPC topology designed for 2.4 GHz operation shows 19–12 dB improvement in phase noise at 10 kHz–1 MHz frequency offset, from the simulations based on 0.25 µm CMOS technology.

Designing robust asynchronous circuit components

Asynchronous circuits require components that display hazard-free operation under normal input conditions. In addition, quasi-delay-insensitive circuits are based on the assumption of isochronic forks, an assumption that can in practice be compromised by threshold variations due to the use of, for example, dynamic or pseudo-dynamic C-gate circuits. In the paper, the authors investigate the severity of these problems in practical circuits. It is shown that threshold variations are much less significant than has previously been assumed, but hazard-free operation is, by contrast, a much more significant problem. Gates with a stack of transistors in series can exhibit charge-sharing problems under specific input sequences that expose hazards that are not evident in the logic description. A design methodology is proposed which overcomes the charge-sharing problem, resulting in more robust circuits.

Leakage control with efficient use of transistor stacks in single threshold CMOS

The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.

Impact of Thermal Nitridation on Microscopic Stress-Induced Leakage Current in Sub-10-nm Silicon Dioxides

By statistically analyzing 28,800 cells of arrayed stacked gate transistors, for the first time, we examine the effectiveness of nitric oxide (NO) and nitrous oxide (N2O) nitridation in the suppression of the microscopic stress-induced leakage current (mSILC) observed in devices on the order of square microns in size. We have found that NO nitridation is more effective in suppressing the mSILC than N2O nitridation and is very promising for the reduction of bit failures. The difference between the SILC observed in devices on the order of square millimeters in size and the mSILC observed in devices on the order of square microns in size is also discussed.

Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations

An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples.

Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations

An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples.

Low cost Pockels cell driver for pulsed solid state lasers

The paper describes a low cost Pockels cell driver for Q-switching flash lamp pumped pulsed solid state lasers. The driver consists of a high voltage pulsed power supply variable from 0 to 5 kV using a standard step up transformer. The pulse width and pulse repetition rate are varied using standard TTL circuits from 50 μs to 2 ms and 1 ppm to 50 Hz, respectively. The pulsed high voltage along with a high voltage switch consisting of a stack of bipolar transistors is used to drive a Pockels cell. The Q-switched pulsed duration measured in Ruby and Nd-YAG lasers are 35 and 15 ns, respectively. The Pockels cell driver performance is consistent for more than 5×10 7 shots.

Low cost fast switch using a stack of bipolar transistors as a pockel cell driver

A fast high voltage switch to discharge a capacitive load using a stack of bipolar junction transistors is described. The switch operating at a voltage of 3.5 kV has a fall time (90%–10%) of ∼2 ns. With a capacitive load (pockel cell) the pulse fall time increases to 6 ns. The life of the stack is >50 million shots.

Complex 3D CMOS circuits based on a triple-decker cell

Presents circuit design for a three-dimensional (3D) CMOS integrated process. This process, with its three stacked transistor channels, leads to the very efficient basic circuits: inverter, selector, and NAND2. These elements are used to build a complete cell library with standard elements like NORs, latches, flip-flops, etc. Special macro blocks such as multipliers, SRAMs and content addressable memories (CAMs) complete the circuit library. Novel concepts and implementations of three-dimensional prefabricated semicustom arrays are introduced. These are the NAND array and the selector array, for which technology-dependent logic synthesis is investigated. Area requirements for static 3-D CMOS logic ranges from 50% down to 33% compared to two-dimensional (2-D) CMOS. These figures include the wiring and are caused by the transistor stacking and the large number of interconnection layers used in the 3D CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Manufacturability of 3D-epitaxial-lateral-overgrowth CMOS circuits with three stacked channels

Epitaxial lateral overgrowth of Si over oxide has been perfected to yield dual-gate transistor stacks with three stacked channels providing high and matched transconductances. Threshold voltage with standard deviation ranging from 50mV to 110mV allow complex 3D logic circuits like parallel multipliers.

Interfacial Shear and Peel Stresses in Multilayered Thin Stacks Subjected to Uniform Thermal Loading

An analytical approach has been developed to evaluate the interfacial shear and peel stresses in multilayered thin stacks subjected to uniform temperature variation. The approach, which is based on an extension of Suhir’s bimetal thermostat model, provides a system of coupled linear second order differential equations used in solving for the interfacial stresses. Once these stresses have been determined, the normal stress in each layer and the deflection of the stack can be readily obtained. Two numerical examples are used to demonstrate the capability of the approach. The first example deals with a five-layered symmetric double-shear solder joint. The results are compared to a nonsymmetric three-layered solder joint to study the effect of bending and the interactions of material properties. One of the interesting features observed is that the maximum interfacial shear stress does not necessarily occur at the edge. The other numerical example is a four-layered transistor stack mounted on a substrate. The structural behavior is analyzed, and the effect of geometric dimension is examined. The present approach is shown to provide more accurate results than those of others based on the same assumptions. In addition, applications of the approach to more general stack configurations are also discussed.

A CMOS OTA for HF filters with programmable transfer function

A CMOS operational transconductance amplifier (OTA) for programmable HF filters is presented. When used in an OTA-C integrator, the unity-gain frequency phase error remains less than 0.3 degrees for frequencies up to more than one tenth of the OTA bandwidth. The OTA has built-in phase compensation, which allows tuning of the transconductance of the OTA (G/sub m/) while maintaining a small phase error. Since this phase error is preserved over the G/sub m/ range of the OTA, the OTA is suitable for filters with a programmable transfer function. Using stacked square-law transistors improves the linearity, DC-gain, and power-consumption properties of the OTA.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Nonlinear and Time Dependent Finite Element Analysis of Solder Joints in Surface Mounted Components Under Thermal Cycling

AbstractA nonlinear and time dependent finite element analysis was performed on two surface mounted electronic devices subjected to thermal cycling. Constitutive equations accounting for both plasticity and creep for 37Pb/63Sn and 90Pb/10Sn solders were assumed and implemented in a finite element program ABAQUS with the aid of a user subroutine. The FE results of 37Pb/63Sn solder joints were in reasonably good agreement with the experimental data by Hall [19]. In the case of 9OPb/1OSn solder in a multilayered transistor stack, the FE results showed the existence of strong peel stress near the free edge of the joint, in addition to the anticipated shear stress. The effect of such peel stress on the crack initiation and growth as a result of thermal cycling was discussed, together with the singular behavior of both shear and peel stresses near the free edge.

Deformation in Multilayer Stacked Assemblies

A linear-elastic analytical model has been developed to describe the deformed geometry of a multi-layered stack assembly subject to thermal loading. The model is based on Timoshenko’s bimetal thermostat analysis [1] and consists of a series of first-order polynomial equations. The radius of curvature, bending moment, force, horizontal and vertical displacements can be determined numerically. These quantities match well with finite element analysis. Calculations for silicon power transistor stacks are presented in order to demonstrate the model capability. The results from this analyitcal model have been found to correlate well with experimental measurements when an appropriate secant modulus is used to represent the nonlinear stress-strain behavior of solder.

Novel Stacked CMOS Process by Local Overgrowth

ABSTRACTA six mask process that yields stacked CMOS circuits is presented. Transistors that were built in reverse order (i. e. the gate first, the gate dielectric second, and only then the channel region) exhibit comparable parameters as conventional devices. A novel device has been built whose current drive is three times that of FETs built in substrate material. The vertical stacking of complementary MOS transistors made it possible to build an inverter with symmetric switching characteristic within the area of a single transistor.

Development of X-ray streak camera electronics at AWRE

The paper reviews a number of X-ray streak cameras developed at AWRE. These cameras are used to provide temporal and one-dimensional spatial or spectral information on X-rays emitted from laser produced plasmas. Two of these cameras have been designed to be combined with other diagnostic instrumentation; one with a Wolter X-ray microscope (×22 magnification) and the other with a Bragg diffraction crystal spectrometer. This latter instrument provides a few eV spectral resolution and ∼15 ps temporal resolution; a typical experimental application at the AWRE HELEN laser facility will be described. The paper describes the circuitry of the bipolar avalanche transistor ramp generator used to drive the streak plates of the cameras. Improvements to this include: (a) increasing the fastest streak rate to ∼10 ps mm−1 by a distributed capacitance network across each of the bipolar stacks of transistors, and (b) reducing the trigger jitter to approximately ±10 ps by the use of a new mix of transistors in the stack and a Raytheon RS 3500 avalanche transistor. Additional improvements have now been added. These include a ‘half-scan’ user facility to aid initial camera timing and direct switching to select the sweep rate of the camera.

Solid state: The case for CMOS: Its low power consumption and many design choices mean that by the decade's end, half of all ICs may be made by this technique

The versatility of CMOS in meeting diverse circuit-design requirements and the reduced cost of processing CMOS are examined from the viewpoint of very large-scale integration. The application of CMOS in dynamic memory is outlined, along with the tradeoffs in optimizing the processing of CMOS devices. The creation of faster CMOS circuits, improved layout density, and interconnections are also highlighted. The necessary advances expected to propel CMOS technology beyond the current level of circuits in the 4-Mb dynamic RAM and 1-b static RAM classes are examined, with particular regard to groove isolation, stacking of transistors, and silicon-on-insulator fabrication.