Transistor Memory Research Articles

Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IL</sub> ) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> scaling mitigate the σMW degradation.

Nanostructured interfacial dipole layers for high-performance and highly stable nonvolatile organic field-effect transistor memory

An interfacial dipole layer formed between the solution-processed charge trapping nanostructures and the active layer enables significant improvement of the charge storage capability and stability.

Polymer electret-based organic field-effect transistor memory with a solution-processable bilayer (PαMS/ cross-linked PVP) gate dielectric

Pentacene based organic field-effect transistors (OFETs) were fabricated, with both cross-linked poly vinyl phenol (CL-PVP) and a bilayer of poly(α-methylstyrene) (PαMS)/ CL-PVP as gate dielectric. The PαMS layer decreases the surface energy of the gate dielectric and increases the hydrophobic nature, which leads to favorable growth of pentacene and the corresponding field-effect mobility, though at a higher gate voltage span, increases three times compared to that of the device with only CL-PVP as the gate dielectric. OFET with bilayer polymer gate dielectric exhibited non-volatile memory behavior with an on-off ratio 103, retention time &gt;103 s and a large memory window of −25 V. The memory effect observed in the device was due to the charge trapping in the PαMS layer, with CL-PVP acting as a blocking dielectric. Our studies indicate that the bilayer dielectric, comprising of solution-processable PαMS/CL-PVP is a good choice for obtaining non-volatile electret memory on an OFET platform.

Steric Hindrance Functionalized Porphyrins as Charge Trapping Elements for Organic Field Effect Transistor Memory

Steric Hindrance Functionalized Porphyrins as Charge Trapping Elements for Organic Field Effect Transistor Memory

High-Performance Aie-Active Poly(Ether Sulfone)S as Polymeric Electret for Energy-Saving Genuine Photonic Transistor Memory

High-Performance Aie-Active Poly(Ether Sulfone)S as Polymeric Electret for Energy-Saving Genuine Photonic Transistor Memory

Vertical‐Pillar Ferroelectric Field‐Effect‐Transistor Memory

In recent years, following trends in developing semiconductors, extensive research has been conducted to develop a hafnia‐based ferroelectric field effect transistor (FeFET) memory. However, its fundamental endurance limitation, which stems from early degradation of the gate insulator, has been a major obstacle to the development of FeFETs, with no clear solution despite attempting various approaches to high‐speed and high‐reliability FeFETs. Herein, a novel metal–ferroelectric–metal–insulator–semiconductor FeFET with vertical‐pillar channel and metal–ferroelectric–metal capacitor (VP‐FeFET) that can adjust the capacitance ratio between the ferroelectric film and gate insulator by modulating the channel height is proposed. The optimized VP‐FeFET exhibits a significantly reduced electric field (≤1.5 MV cm−1) through the gate insulator, resulting in a substantially enhanced FeFET endurance. Furthermore, the proposed FeFET achieved a large memory window of ≈5 V and a high program/erase speed of ≈100 ns. These merits are achieved without increasing the footprint of the FeFET device. This approach to high‐performance FeFET can be applied extensively to next‐generation nonvolatile memory devices.

Monolithic Integration of Sn-Doped IGZO Transistor and Ferroelectric Memory for High-Density Memory Applications

Monolithic Integration of Sn-Doped IGZO Transistor and Ferroelectric Memory for High-Density Memory Applications

Ultrathin Metal–Organic Framework Nanosheets as Nano‐Floating‐Gate for High Performance Transistor Memory Device

AbstractMetal–organic framework (MOF) is an emerging important class of functional materials in the fields of information storage, wearable electronics and optoelectronic devices. The interaction of electrons or holes with MOFs is important for the systematic exploration of MOFtronics and to investigate the related structure–performance correlation. Herein, MOF flat nanosheets of copper tetrakis(4‐carboxyphenyl)porphyrin with sub‐10 nanometer scale in thickness are employed as the charge‐trapping layer in organic field‐effect floating‐gate transistor memory device fabricated by an air–liquid interfacial assembly and subsequent stamping operation. As charge trapping sites, MOF nanosheets with ultrathin nanoporous arrays significantly improve in comparison with the memory device using its counterpart ligand of tetrakis(4‐carboxyphenyl)porphyrin as the trapping elements. As compared to the reported widely applied nanofloating gate materials of gold nanoparticles, graphene, or macromolecular nanomaterials, a short pulse (≈20 ms) on the device gets a considerable memory window of ≈37.5 V at a programming voltage of ‐80 V, with a retention time longer than 104 s and good ON/OFF ratio of &gt;103. Furthermore, the hybrid structure composed of metal and organic components endows it with electron and hole trapping capability. This work could push forward the fundamental research of organic–inorganic–hybrid electronics in future microelectronic research.

Characterizing Ferroelectric Properties of Hf0.5Zr0.5O2 From Deep-Cryogenic Temperature (4 K) to 400 K

Ferroelectric Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) thin film has obtained considerable attention for emerging non-volatile memory (eNVM) and synaptic device applications. To our best knowledge, the polarization switching of HZO has not been comprehensively investigated in wide-ranging temperatures from deep-cryogenic 4 K to elevated temperature 400 K within the same set of test structures. In this work, we experimentally characterize the reliability effects such as endurance (wake-up, fatigue, and breakdown), retention (including imprint), and small-signal response of the HZO capacitor from the lowest temperature reported (4 K) to the elevated temperature (400 K). We demonstrate one of the highest endurance cycles <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ &gt; 3.5\times 10^{10}$ </tex-math></inline-formula> among reported TiN/HZO/TiN capacitors with negligible wake-up/fatigue effects or retention degradation, all obtained at 4 K. Based on the experimental results, we further simulated ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistor (FeFET) to evaluate their potentials as cryogenic memories.

Thickness Effect of Polar Polymer Films on the Characteristics of Organic Memory Transistors

Thickness Effect of Polar Polymer Films on the Characteristics of Organic Memory Transistors

Multiband Photoresponding Field‐Effect Transistor Memory Using Conjugated Block Copolymers with Pendent Isoindigo Coils as a Polymer Electret (Adv. Electron. Mater. 12/2021)

Isoindigo Coils In article number 2100655, Yan-Cheng Lin, Yang-Yen Yu, Wen-Chang Chen, and coworkers present a series of poly(fluorene) based conjugated block copolymers with pendent isoindigo coils applied into fieldeffect transistor memory as a photoactive polymer electret capable of responding to panchromatic and Ultraviolet-C light.

USING PERCOLATIVE CRYSTALLINE 0.3 CUO/PVDF NANOCOMPOSITE GATE DIELECTRIC FOR FABRICATING HIGH-EFFECT MOBILITY THIN FILM TRANSISTOR OPERATING AT LOW VOLTAGE

Thin-film transistor (TFT) with various layers of crystalline Poly-vinylidene fluoride (PVDF)/CuO percolative nanocomposites based on Anthracene as a gate dielectric insulator have been fabricated. A device with excellent electrical characteristics at low operating voltages (&lt;1V) has been designed. Different layers (L) of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constants (εr). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films have been investigated. This device was showed highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of -1.6V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such a High-ε three layered (3L) PVDF/CuO gate dielectric appears to be highly promising candidates for organic non-volatile memory, sensor and field-effect transistors (FETs).

3D Steric Bulky Semiconductor Molecules toward Organic Optoelectronic Nanocrystals

With minimal defects, few grain boundaries, and high-performance optoelectronic characteristics, organic semiconductor nanocrystals (OSNCs) have emerged as promising solutions for miniaturized organic devices and related optoelectronic circuits. To realize this, it is crucial that the OSNCs should possess desired morphologies and unique optoelectronic attributions. After the planar π-conjugated building blocks, the steric bulky molecules with a three-dimensional (3D) framework enable the multiscale self-assembly architectures and superior charge storage properties, as well as high-performance optoelectronic applications, such as organic transistor memory, organic light-emitting diodes, organic lasers and organic photovoltaic cells. However, this type of 3D steric bulky molecule-based OSNCs are not easily to get, and molecular design principles must be developed. In this Review, recent advances in the efficient theories that have arose in building varied nanoarchitectures of 3D steric bulky molecule-based OSNCs, especially the 2D and 3D in morphology, are highlighted. The obtained steric OSNCs exhibited rich optoelectronic properties, including the charge storage, ion transmission, crystallization-enhanced emission, and so on. Further architectural optimization of the steric OSNCs to cater for optoelectronic device based on them is necessary to strive to develop this research direction.

Volatility Transition from Short‐Term to Long‐Term Photonic Transistor Memory by Using Smectic Liquid Crystalline Molecules as a Floating Gate

AbstractRod‐like molecules with liquid crystalline phase transitions show highly ordered stacking and orientation, which is promising as the floating gate electret in high‐performance photonic field‐effect transistor (FET) memory. In this work, a series of rod‐like molecules, alkyl‐dinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene (Cn‐DNTT), are investigated with a smectic liquid crystalline phase transition. The photonic FET memory featuring these rod‐like molecules is correlated with their morphology and crystallographic properties. A volatility transition from short−term to long−term memory behavior is found by utilizing the smectic liquid crystalline phase transitions (SmX, X = H, K, E) to orient the stacking in the floating gate. Accordingly, the annealed 2,9‐didecyldinaphtho[2,3‐b:2′,3′‐f]thieno[3,2‐b]thiophene (C10‐DNTT) polycrystalline film with the optimized alkyl chain length achieved preferential end‐on orientation associated with the herringbone‐type stacking to store charges during photowriting, along with effective charge tunneling for the trapped charges during electrical erasing. Therefore, the resultant photonic FET memory provided a superior ON/OFF current ratio of up to 105 with retention of 104 after 104 s. The results demonstrate that rod‐like molecules with smectic liquid crystalline phase and highly ordered orientation have great potentials for developing high‐performance photonic FET memory.

Liquid Crystalline Rylenediimides with Highly Order Smectic Layer Structure as a Floating Gate for Multiband Photoresponding Photonic Transistor Memory

AbstractWith the growing demands of light fidelity technology, photonic transistor memory has gained considerable attention for next‐generation optoelectronic devices. In this work, alkylated rylenediimides of 2,9‐diphenethylanthra[2,1,9‐def:6,5,10‐d“e”f]diisoquinoline‐1,3,8,10(2H,9H)‐tetraone (C8‐PDI) and 2,7‐dioctylbenzo[lmn][3,8]phenanthroline‐1,3,6,8(2H,7H)‐tetraone (C8‐NDI), and pyromellitic diimide of 2,6‐dioctylpyrrolo[3,4‐f]isoindole‐1,3,5,7(2H,6H)‐tetraone (C8‐PMDI) have been used as floating gate electrets in the photonic field‐effect transistor‐type memory. The structure‐optics‐performance relationship of these rod‐like molecules has been systematically studied, and the memory device exhibited a decent response to photowriting and electrical erasing processes, owing to the 3D ordered smectic layer structure and brickwork stacking. Therefore, an evenly distributed photogating moiety, efficient exciton dissociation associated with decent carrier tunneling and charge trapping can be obtained. Among them, the sought‐after C8‐NDI presents favorable energy level alignment, multiband photoresponding, and an optimal block ratio. The fabricated photonic memory with C8‐NDI electret presented a remarkable memory switchability with a memory ratio of 104 and a stable memory ratio of 105 over 10,000 s. To the best of knowledge, this is the first work to utilize rylenediimides based liquid crystals as an efficient charge blocking electret, and these findings open an avenue for designing rod‐like molecules with highly ordered liquid crystalline properties in the ultrafast photomemory devices.

Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate

Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM) device exhibits outstanding memory properties, including tremendous memory window (∼85 V), superhigh memory on/off ratio (∼109), long data retention (over 10 years) and eminent multilevel storage behavior, which are among the optimal performances in NFGM devices based on organic field effect transistors. Additionally, the device displays photoinduced-reset characteristic with low energy consumption erasing operation. This study provides novel avenues for the manufacture of simple and low-cost data storage devices with outstanding memory performance, multilevel storage behavior and suitability as platforms for integrated circuits.

(Invited) Ferroelectric Hafnium Oxide for Non-Volatile Memory Applications: From Single Capacitors to Memory Arrays

This year marks the 10th anniversary of the public announcement of the discovery of ferroelectricity in HfO2-based thin films. Tremendous strides have been made in both the physical understanding and the technological use of ferroelectric HfO2. These unique fluorite-structured ferroelectrics have outstanding potential for commercial applications due to their scalability, CMOS-compatibility, and facile manufacturability. Such advantages make ferroelectric HfO2 particularly attractive for nonvolatile memories technologies such as ferroelectric random access memory (FRAM) and ferroelectric field effect transistors. Due to the wide variety of conditions in which ferroelectricity can emerge in HfO2 thin films, there has been a vast effort by the international scientific community to enhance and optimize the ferroelectric properties using a wide variety of approaches. Advancements in thin film ferroelectric capacitor and memory array technologies are therefore progressing rapidly.The structural properties of HfO2 are a major focal point for technology development because the competition between several crystalline phases in HfO2 thin films can have a major impact on device performance. For thin film memory capacitors, stabilizing the polar orthorhombic phase and eliminating secondary paraelectric phases is paramount in achieving robust polycrystalline HfO2 ferroelectrics. Doping and the presence of a capping electrode during crystallization have been extensively demonstrated to influence the emergence and stability of the ferroelectric orthorhombic phase. Greater attention has been placed recently on the thin film growth conditions in atomic layer deposition and physical vapor deposition, especially with regard to the oxidation conditions that have been shown to have a substantial impact on the device performance of ferroelectric HfO2 and Hf0.5Zr0.5O2 capacitors. Composition, film growth, and the crystallization processes are critical aspects for thin film ferroelectric capacitor development and the latest developments will be comprehensively reviewed in the context of how the material properties relate to nonvolatile memory performance.Developments in thin film HfO2 ferroelectric capacitors are now coming to fruition with the emergence of ferroelectric random access memory arrays and demonstrators. Thin film ferroelectric HfO2 based capacitors are successfully being demonstrated in back-end-of-line (BEOL) processes at the 130nm CMOS technology. The performance of these early demonstrator memory arrays show very promising long term data retention, large memory windows with good statistical distributions, and projections for area scaling to nanoscale dimensions. The transition from large-scale micron-sized laboratory devices to smaller scale integrated capacitors has proven to be a major step forward in endurance cycling with >1011 cycles being reported in memory arrays. The most recent integration of thin film ferroelectric HfO2 capacitors into FRAM memory arrays and what future developments are expected for HfO2 ferroelectric random access memories will be presented. Figure 1

Organophosphine‐Sandwiched Copper Iodide Cluster Enables Charge Trapping

AbstractHerein, we report a feasible molecular design of the binuclear clusters featuring the n‐p‐n heterojunction of biligand‐sandwiched inorganic units, which can be used as the effective charge trapper in ambipolar transistor memories with the large memory windows and the energy‐saving operation. We found that the hole confinement on the p‐type inorganic units is enhanced by spatial electronic anisotropy provided by the peripheral n‐type organic phosphine ligands. The steric hindrance of the coordination sites, the insulating effect of the carbon‐phosphorous single bonds and the parallel dual‐ligand coordination mode jointly elongate the interunit distances to nanometer scale and restrain the intramolecular electronic communications, leading to the tunable and reliable charge trapping. Our results show that the spatial effect is crucial to further amplifying the electronic differences between organic and inorganic units for function enhancement.

Organophosphine-Sandwiched Copper Iodide Cluster Enables Charge Trapping.

Herein, we report a feasible molecular design of the binuclear clusters featuring the n-p-n heterojunction of biligand-sandwiched inorganic units, which can be used as the effective charge trapper in ambipolar transistor memories with the large memory windows and the energy-saving operation. We found that the hole confinement on the p-type inorganic units is enhanced by spatial electronic anisotropy provided by the peripheral n-type organic phosphine ligands. The steric hindrance of the coordination sites, the insulating effect of the carbon-phosphorous single bonds and the parallel dual-ligand coordination mode jointly elongate the interunit distances to nanometer scale and restrain the intramolecular electronic communications, leading to the tunable and reliable charge trapping. Our results show that the spatial effect is crucial to further amplifying the electronic differences between organic and inorganic units for function enhancement.

Porous p–n junction-induced memory characteristics in low-voltage organic memory transistors

Low-voltage organic memory transistors (LOMTs) as data storage units are crucial for the advancements of future flexible electronics. However, charge storage mechanism remains a great challenge. In this work, we used poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno(3,2-b)thiophene) (PBTTT-C14) as the active layer and incorporated poly(methyl methacrylate) (PMMA) with the PBTTT-C14 through a simple blending process to fabricate LOMTs with porous structure. The function of the porous structure was to improve the carrier traps, which can effectively capture the holes at the charge trapping regions during the programming process. A maximum threshold voltage shift of 1.01 V was achieved when the weight ratio of PBTTT-C14 and PMMA is 7:3, and the LOMTs were operated under the programming process of −4 V/1 s. Impedance-admittance analyses were used to investigate the interfacial trap density of charge trapping regions, which is a supporter of the programming capability of LOMTs. An ultrathin dioctyl perylene tetracarboxylic diimide film was deposited on the active layer with porous structure in LOMTs. This film can increase the carriers’ erasing capability. A wide memory window of 1.64 V was obtained in LOMTs when the devices are operated under the erasing process of bias pulse of 3 V/1 s with the assistance of 2.5 mW cm−2 light irradiation. This study facilitates the development of high-performance LOMT device in fresh-type memory.