Transistor Memory Devices Research Articles

One Transistor Ferroelectric Memory Devices with Improved Retention Characteristics

We have fabricated Pb5Ge3O11 (PGO) MFMPOS (M: metal, F: ferroelectrics, P: polysilicon, O: oxide, S: silicon) memory transistor devices using metal organic chemical vapor deposition (MOCVD) selective deposition, damascene structure and chemical mechanical planarization (CMP) processes. These processes have no need to etch the ferroelectric material. As a result, etching-induced damages are avoided. The one-transistor memory devices show memory windows around 2–3 V. The memory windows are almost saturated from operation voltage of 3 V. For the one transistor memory device, after writing the “off” state (-5 V), the drain current (ID) at a VD of 0.1 V and a VG of 0, 0.5, and 1 V is about 2×10-14 A. After writing the “on” state (+5 V), the drain current (ID) at a VD of 0.1 V and a VG of 0, 0.5, and 1 V is about 1×10-5 A. The ratio of the “on” state current to the “off” state current is close to 9 order. The 1 T devices show very good memory characteristics. The one-transistor memory devices also show very good retention properties.

Integration Processes and Properties of One Transistor Memory Devices

ABSTRACTMFMPOS (Metal, Ferroelectrics, Metal, Polysilicon, Oxide, and Silicon) one-transistor (1T) ferroelectric memory devices have been fabricated. However, the yield of 1T-memory devices is lower. We find that the main problems of 1T MFMPOS memory devices are shorts, opens, no memory window, smaller memory windows and blank. In order to solve these problems, we studied the reasons resulted in the problems. Then, the integration processes for one transistor memory device were optimized. Fabrication of nMOSFET 1T memory devices starts with shallow trench isolation (STI) on p-type Si. A gate oxide is thermally grown after p-well implantation. Phosphorus ions were implanted after polysilicon gate definition for the formation of self-aligned source, drain, and n-type floating gate. A damascene process using MOCVD PGO deposition and chemical mechanical polishing (CMP) were used to avoid etching damage. Electrodes for the ferroelectric capacitor, i.e., the floating Ir bottom electrode and Pt top electrode, are deposited by E-Beam evaporation. The area ratio of the top and floating gate electrodes is 1:1. After inter-level dielectric (ILD) deposition, contact etching stops on Pt at gate and on Si at source/drain (S/D) without difficulty because of high etch rate selectively to the Pt. Finally, the high quality 1T memory devices have been made. The one-transistor memory devices showed memory windows around 2 – 3V. The memory windows are almost saturated from operation voltage of 3V. The ratios of “on” state current to the “off” state current are closed to 8 – 9 orders. The one-transistor memory devices also show a very good memory characteristics and retention properties.

Integration Processes and Properties of One Transistor Memory Devices

ABSTRACTMFMPOS (Metal, Ferroelectrics, Metal, Polysilicon, Oxide, and Silicon) one-transistor (1T) ferroelectric memory devices have been fabricated. However, the yield of 1T-memory devices is lower. We find that the main problems of 1T MFMPOS memory devices are shorts, opens, no memory window, smaller memory windows and blank. In order to solve these problems, we studied the reasons resulted in the problems. Then, the integration processes for one transistor memory device were optimized. Fabrication of nMOSFET 1T memory devices starts with shallow trench isolation (STI) on p-type Si. A gate oxide is thermally grown after p-well implantation. Phosphorus ions were implanted after polysilicon gate definition for the formation of self-aligned source, drain, and n-type floating gate. A damascene process using MOCVD PGO deposition and chemical mechanical polishing (CMP) were used to avoid etching damage. Electrodes for the ferroelectric capacitor, i.e., the floating Ir bottom electrode and Pt top electrode, are deposited by E-Beam evaporation. The area ratio of the top and floating gate electrodes is 1:1. After inter-level dielectric (ILD) deposition, contact etching stops on Pt at gate and on Si at source/drain (S/D) without difficulty because of high etch rate selectively to the Pt. Finally, the high quality 1T memory devices have been made. The one-transistor memory devices showed memory windows around 2 – 3V. The memory windows are almost saturated from operation voltage of 3V. The ratios of “on” state current to the “off” state current are closed to 8 – 9 orders. The one-transistor memory devices also show a very good memory characteristics and retention properties.

Comparison of MFMOS and MFOS One Transistor Memory Devices

Comparison of MFMOS and MFOS One Transistor Memory Devices

Comparison of MFMOS and MFOS One Transistor Memory Devices

Pt/PGO/HfO 2 /Si (MFOS) and Pt/PGO/Ir/Polysilicon/SiO 2 /Si (MFOS) and Pt/PGO/Ir/Polysilicon/SiO 2 /Si (MFMPOS) one-transistor devices have also been fabricated. The working functions and properties of both Pt/PGO/HfO 2 /Si (MFMPOS) one-transistor devices have also been measured. Compared with PGO MFOS one-transistor devices, PGO MFMPOS one-transistor devices showed lower operation voltage, smaller sub-threshold voltage swing, larger memory windows and better retention properties, but more difficult integration processes. In order to find the reasons for the different properties between MFOS and MFMPOS one-transistor devices, the relationship between the properties and structures, including interface and microstructure, has been investigated and discussed.

Ferroelectric Pb5Ge3O11 MFMOS capacitor for one transistor memory applications

The basic mechanism for an one transistor memory device has been studied. Many ferroelectric materials such PbZrxTi1−xO3 (PZT), SrBi2Ta2O9 (SBT), Pb5Ge3O11 (PGO) etc. were analyzed for this application. Because of its low remanent polarization and low dielectric constant, the c-oriented Pb5Ge3O11 thin film was selected for one-transistor memory applications. Pb5Ge3O11 thin films have been prepared using MOCVD and RTP (Rapid Thermal Process) post-annealing. Lead bis-tetramethylheptadione [Pb(thd)2] and germanium ethoxide [Ge(OC2H5)4] were used as the precursors. The Pb5Ge3O11thin films were deposited onto Ir/Ti/SiO2/Si wafers to measure their compositions, phase formation, microstructure and ferroelectric properties. The extremely highly c-oriented Pb5Ge3O11 thin films showed good ferroelectric and electrical properties. A 300 nm thick PGO thin film exhibited a square and saturated hysteresis loop with 2Pr of 3.98 μC/cm2, 2Ec of 128 KV/cm at an applied voltage 5V, leakage current of 5.1×10−7 A/cm2 at 100 KV/cm, and dielectric constant of close to 36. The c-axis oriented Pb5Ge3O11 thin film also exhibited very good retention properties. The experimental results showed that a Pb5Ge3O11 MFMOS gate stack is suitable for one-transistor memory applications.

Integration Processes and Properties of Pt/Pb5Ge3O11/(Zr, Hf)O2/Si One Transistor Memory Devices

AbstractThe basic mechanism for one transistor memory device has been studied. Ferroelectric material, Pb5Ge3O11 (PGO) was selected for MFOS (M: Metal, F: Ferroelectrics, O: oxide, S: silicon) memory transistor fabrication. Processing of one-transistor memory devices dealt with the following issues: decomposition of ferroelectric materials, the etching damage of ferroelectric materials, the forming gas annealing damage of ferroelectric materials, the selective deposition of ferroelectric materials, the alignment for device making processes. The integration processes for one transistor memory device have been optimized to reduce process-induced damages. The gate dielectric material is (Zr, Hf)O2. Extremely high c-axis oriented Pb5Ge3O11 thin films were successfully deposited on high k gate oxide. Memory transistors having 0.6, 3 and 10μm channel length and 10 μm channel width have been fabricated. The memory windows are around 1 - 2V. The memory windows are almost saturated from operation voltage of 4V. After programming at -5V (on “off” state), the drain current (ID) at VD of 1V and VG of 2.5 V is about 1.15 ×10−10A. After programming at 5 V (on “on” state) the drain current (ID) at VD of 1V and VG of 2.5 V is measured about 6.4 ×10−8 A, which was 2.5 order higher than that of “off” state.

Characteristics of Memory Window and Retention Properties of One Transistor Memory Devices

AbstractPb3Ge5O11(PGO) metal-ferroelectric-metal-oxide-semiconductor (MFMOS) and metalferroelectric-oxide-semiconductor (MFOS) one-transistor ferroelectric memory devices have been fabricated. The memory windows of the memory transistors can be characterized in terms of MFMOS or MFOS capacitor and the threshold voltages of the transistor. The retention properties of one-transistor memory devices can be measured from the changes of the capacitance of MFMOS or MFOS capacitors. Alternatively the retention properties can be evaluated from the threshold voltages or drain currents of the transistor with retention time. There are inconsistencies between the capacitor data and the transistor data. In this paper, we present the memory windows and retention properties of MFOS and MFMOS one-transistor memory devices measured with various methods. The different results obtained from various methods and device structures will be discussed.

The properties of mfmos one transistor memory devices

Integration processes for one transistor memory device have been optimized to reduce process-induced damages. One-transistor ferroelectric memory devices with MOCVD Pb5Ge3O11 (PGO) MFMOS memory cells have been fabricated. The hysteresis loop of a 300 nm thick PGO thin film capacitor exhibited a square and saturated form with 2Pr of about 4 μC/cm2 and 2Ec of 134 KV/cm at an applied voltage of 5V. The capacitor leakage current is 1– 5 × 10−7 A/cm2 at 100KV/cm. The peak dielectric constant is around to 35 – 45. The c-axis oriented Pb5Ge3O11 thin film also showed very good retention properties. The 1T-memory devices showed memory windows around 2V. The memory windows were almost saturated when the operation voltage is 2V. After programming to -4 V (on “off'’ state), the drain current (Id) of the memory transistor operated at Vd of 0.1V and Vg of 0.5 V is about 1×10−8 A. After programming to 4V (on “on” state) the drain current (ID) of the device operated at VD of 0.1V and VG of 0.5 V is about 1 ×10−6 A, which is about 100 times high than that of “off state. The device also exhibits excellent imprint and fatigue properties.

Characteristics of Narrow Channel MOSFET Memory Based on Silicon Nanocrystals

Metal-oxide-semiconductor field-effect transistor (MOSFET) memory devices with silicon-nanocrystal-based floating gates on a narrow channel have been fabricated. Electrical measurements have been performed in the temperature range of 20–300 K for devices of various channel dimensions. Large threshold voltage shifts are obtained, being obviously dependent on channel width, and independent of channel length. It is experimentally found that the threshold voltage shift and charge retention characteristics are almost independent of temperature. Furthermore, single electron charge/discharge processes are observed in the device with the narrowest channel.

Ferroelectric C-Axis Oriented Pb5Ge3O11 Thin Films for One Transistor Memory Application

AbstractOne transistor memory devices have been proposed recently. To meet the needs of one transistor memory applications, C-axis oriented Pb5Ge3O11 (PGO) thin films were prepared using metalorganic chemical vapor deposition (MOCVD) and rapid thermal processing (RTP). It was found that the nucleation of C-axis Pb5Ge3O11 phase started at a deposition temperature below 400°C and grain growth dominated at 500°C or above. With increasing annealing temperature, the remanent polarization (Pr) and coercive field (Ec) values increased, and the hysteresis loops of the Pb5Ge3O11 films were well saturated and symmetrical after the post-annealing. The C-axis PGO thin film showed good ferroelectric properties at 5V: 2Pr and 2Ec values were 2.0 - 4.0 µC/cm2 and 90 - 110 kV/cm, respectively. The films also showed excellent fatigue characteristics: no fatigue was observed up to 1 × 109 switching cycles. The retention and imprint properties have also been studied. The leakage currents of the PGO films were 2 - 5 × 10−7 A/cm2 at 100 kV/cm and dielectric constants were 40 - 70. The high quality MOCVD Pb5Ge3O11 films can be used for single transistor ferroelectric memory devices.

Analysis of stored charge volatility in an MAOS memory element

An exact analytical solution is derived for the dynamics of the interface discharging process for a metal/Al 2O 3/SiO 2/Si (MAOS) insulated gate field effect transistor memory device. The predicted results are shown to be in good agreement with experimental data. It is seen that the discharge current is through the Al 2O 3 rather than the SiO 2 layer for the self-bias discharging conditions usually encountered. At temperatures above about 200°C the ohmic component of the Al 2O 3 current controls the volatility, whereas at lower temperatures (including room temperature) the Poole-Frenkel current is important. Hence the discharge process is highly temperature sensitive. The theory also predicts that the usually quoted half-lives of the interface charge at room temperature (of the order of 10 15 h based on the log time dependence) are gross overestimates; a more realistic value based on the exact theory is about 10 4–10 5 h.