Transistor-level Simulation Results Research Articles

Model of a switched-capacitor programmable voltage reference for ultra low-power applications

This paper proposes an analytical model for the optimized design of a switched-capacitor programmable voltage reference (SC-PVR). This PVR topology guarantees a straightforward design, easy portability across different technology nodes, and does not require any special technology option. The developed model allows the study of the trade-offs and the a priori evaluation of the system performance. The circuit design optimization is carried out with MATLAB, and it permits SC-PVR to achieve current consumptions of few tens of nanoampere, with a voltage ripple specification of 500 μV. An SC-PVR has been designed in 65-nm CMOS technology, with a sizing extracted by the model optimization. Transistor-level simulation results are aligned with MATLAB results and confirm that the investigated architecture is suitable for ultra low-power applications.

Capacitance-to-voltage converter employing parallel-series passive charge integrator for low noise power efficient MEMS capacitive sensor

Parallel-series passive charge integrator (PSPI) based capacitance-to-voltage converter (CVC) is proposed in this paper to reduce the noise floor of readout circuit for MEMS capacitive sensor with high power efficiency in terms of the figure of merit (FoM). For MEMS capacitive accelerometer, open-loop structure is preferred for its low power consumption. However, in the open-loop structure, the capacitance variation of sensing element is limited to femto-farad level in order to overcome nonlinearity. As a result, the thermal noise from parasitic capacitance becomes significant, which leads to low SNR. Traditional oversampling method can reduce the parasitic-induced noise, but leads to low power efficiency. In this work, the PSPI-CVC is proposed to reduce the parasitic-induced noise with high power efficiency. The PSPI-CVC is designed by a commercial 0.18 μm CMOS process. The transistor-level simulation results show that, compared to the traditional CVC, the PSPI-CVC can improve the SNR by 24 dB without increase of the power consumption. Compared with the other similar works, the proposed readout circuit achieves competitive FoM1 (FoM1 =20.2pJ)and the best FoM2 (FoM2).

Hardware Trojan Attack in Embedded Memory

Static Random Access Memory (SRAM) is a core technology for building computing hardware, including cache memory, register files and field programmable gate array devices. Hence, SRAM reliability is essential to guarantee dependable computing. While significant research has been conducted to develop automated test algorithms for detecting manufacture-induced SRAM faults, they cannot ensure detection of faults deliberately implemented in the SRAM array by untrusted parties in the integrated circuit development flow. Indeed, such hardware Trojan attacks represent an emerging security threat. While a growing body of research addresses Trojan designs in logic circuits, little research has explored hardware Trojan attacks in embedded memory arrays [20]. In this article, we propose a new class of hardware Trojans targeting embedded SRAM arrays. The Trojans are designed to evade industry standard post-manufacturing tests while enabling attacks targeting various system hardware components during deployment. Transistor-level simulation results demonstrate minimal impact on SRAM power, performance, and stability while Trojans are not activated. We also prove the feasibility of Trojan insertion in foundries by showing the proposed layouts that preserve the SRAM cell footprint and incur zero silicon area overhead. Finally, we elaborate on several system-level attacks that can leverage these Trojans to compromise security and privacy.

Classification and Design Space Exploration of Low-Power Three-Stage Operational Transconductance Amplifier Architectures for Wide Load Ranges

Since operational transconductance amplifiers (OTAs) form the basic building blocks of many analog systems, the compensation of three-stage OTAs has attracted a lot of attention in the literature. Many different solutions to the stability problem of such OTAs have been proposed over the past 20 years, with each solution exhibiting different properties or targeting a different application. This work surveys a broad selection of previously reported architectures and proposes a novel classification scheme that exposes features common to seemingly different compensation architectures and serves as a guideline for which type of OTA is suitable for a given application. In addition, a novel figure of merit (FoM) is proposed to guide the designer in deciding which OTA architecture suits the tradeoffs specific to the application at hand. Theoretical discussions are further reinforced by transistor-level simulation results.

PSS4: Four-Phase Shifted Sinusoid Symbol Signaling for High Speed I/O interconnects

Various signaling techniques have been considered for I/O interconnects at 25 Gb/s or higher. However, they either suffer from high baud rate, as in the case of NRZ, or an excess signal-to-noise ratio penalty, as in the case of PAM-4. To overcome these problems, a four-phase shifted sinusoid symbol (PSS-4) signaling method is proposed that can be readily applied to high-speed I/O transceivers. By using PSS-4, the SNR penalty can be reduced from PAM-4; our theoretical analysis has revealed that the SNR performance of the PSS-4 is 6.5 dB better than that of PAM-4 with comparable bandwidth. The transistor-level simulation results have shown that PSS-4 has an average of twice larger vertical eye opening than PAM-4. In addition, the supply voltage sensitivity of PSS-4 is 55% and 20% less than that of PAM-4 and NRZ, respectively, and the power consumption of PSS-4 is 13.5% lower than that of PAM-4.

An Improved Solution for the Fast-Locking All Digital SAR DLL

All digital successive approximation register-controlled delay-lock loops (SAR DLL) are widely used in system-on-chip to solve the clock generation and skew problems for their fast-locking characteristic. However, the conventional SAR DLL has the dead lock problem. So many improved solutions are proposed to solve the dead lock problem. Based on the resettable delay line, improved SAR controller and phase comparator are depicted. By these, a harmonic-free and fast-locking all digital SAR DLL without dead lock is implemented. Post-layout transistor-level simulation results show that the lock-in and relock-in time are both within N cycles of input clock for N-bit SAR controller. The dead lock problem of the conventional SAR DLL is eliminated very well.

A Frequency Model of a Continuously Driven Clocked CMOS Comparator

A frequency model of a continuously driven clocked CMOS comparator with the effect of the input signal during regeneration is presented. The model utilizes a small-signal linear model derived from the theoretical analysis of the comparison error caused by the transition from the tracking mode to the regeneration mode. The comparison error voltage is a function of input signal frequency and is represented with the transfer function. The correctness of the model is assured by several transistor-level simulation results. The model provides a valuable insight for the design of high-speed comparators.

A radiation-hardened-by-design technique for improving single-event transient tolerance of charge pumps in PLLs

A radiation-hardened-by-design (RHBD) technique for phase-locked loops (PLLs) has been developed for single-event transient (SET) mitigation. By presenting a novel SET-resistant complementary current limiter (CCL) and implementing it between the charge pump (CP) and the loop filter (LPF), the PLL's single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 93.1 % and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.

Modified Model for Settling Behavior of Operational Amplifiers in Nanoscale CMOS

An accurate time-domain model for the settling behavior of folded-cascode operational amplifiers is presented. Using a velocity-saturation model for MOS transistors makes the proposed model suitable for nanoscale CMOS technologies. Both linear and nonlinear settling regimes and their combination are considered. Transistor-level HSPICE simulation results of a fully differential single-stage folded-cascode amplifier using BSIM4v3 models of a standard 90-nm CMOS process are presented to verify the accuracy of the proposed models.

A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique

This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 μm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

Structure of complex elliptic Gm-C filters suitable for fully differential implementation

The complexification method of Gm-C filters is presented. Unlike the previously reported method, the proposed method is suitable for the realisation of the fully differential complex Gm-C filters with finite zeros. Based upon the proposed method, complexification of the third-order elliptic Gm-C filter is demonstrated and the practical transistor-level simulation results of the resulting complex filter are also given.

Bipartitioning and encoding in low-power pipelined circuits

In this article, we present a bipartition dual-encoding architecture for low-power pipelined circuits. We exploit the bipartition approach as well as encoding techniques to reduce power dissipation not only of combinational logic blocks but also of the pipeline registers. Based on Shannon expansion, we partition a given circuit into two subcircuits such that the number of different outputs of both subcircuits are reduced, and then encode the output of both subcircuits to minimize the Hamming distance for transitions with a high switching probability. We measure the benefits of four different combinational bipartitioning and encoding architectures for comparison. The transistor-level simulation results show that bipartition dual-encoding can effectively reduce power by 72.7% for the pipeline registers and 27.1% for the total power consumption on average. To the best of our knowledge, it is the first work that presents an in-depth study on bipartition and encoding techniques to optimize power for pipelined circuits.

Digital frequency tuning technique based on current division for integrated active RC filters

A novel digital frequency tuning technique is presented for integrated active RC filters. Instead of varying the values of the capacitors or resistors as in traditional approaches, the proposed technique achieves frequency tuning by dividing the currents that flow from resistors to virtual grounds. Current division is performed through a digitally programmable current division network added at each virtual ground. The technique features compact size, wide tuning range and high linearity. Transistor level simulation results are presented to demonstrate the technique.

An inductorless CMOS realization of Chua’s circuit

In this paper, an inductorless CMOS realization of Chua’s circuit [IEEE Trans. Circ. Syst.––I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua’s circuit and can generate Rossler or double-scroll attractors by changing a single capacitor’s value. Variables are represented in the current domain to facilitate adding or subtracting variables. New G m– C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as ±1.5 V. Transistor-level simulation results using PSpice in 0.5 μm Mietec process are presented.

Exploiting Data‐dependencies in Ultra Low‐power DSP Arithmetic

Strategies for the design of ultra low power multipliers and multiplier‐accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data‐dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic‐logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry‐save array and deliver energy consumption which is also heavily data‐dependent.Energy efficient adaptations for handling two′s complement operands are introduced. Area overheads of the proposed designs are estimated and transistor level simulation results of signed and unsigned multipliers as well as a signed multiplier‐accumulator are given.Normalized comparisons with other designs show our approach to use less energy than other published multipliers.