Abstract

Since operational transconductance amplifiers (OTAs) form the basic building blocks of many analog systems, the compensation of three-stage OTAs has attracted a lot of attention in the literature. Many different solutions to the stability problem of such OTAs have been proposed over the past 20 years, with each solution exhibiting different properties or targeting a different application. This work surveys a broad selection of previously reported architectures and proposes a novel classification scheme that exposes features common to seemingly different compensation architectures and serves as a guideline for which type of OTA is suitable for a given application. In addition, a novel figure of merit (FoM) is proposed to guide the designer in deciding which OTA architecture suits the tradeoffs specific to the application at hand. Theoretical discussions are further reinforced by transistor-level simulation results.

Highlights

  • With the continued aggressive scaling of CMOS technologies, the speed of digital circuits has been increasing and their power consumption decreasing

  • For a specified GBW, the parameter ω0 correlates with power consumption through the transconductances gm2 and gm3. This is true for other three-stage operational transconductance amplifiers (OTAs) as well since ω0 relates to how far the non-dominant poles are pushed beyond the GBW

  • The OTA cores were implemented in a standard 0.18 μm CMOS technology with targeted values for gm1, gm2 and gm3 set to 10 μS, 50 μS and 500 μS, respectively

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Summary

Introduction

With the continued aggressive scaling of CMOS technologies, the speed of digital circuits has been increasing and their power consumption decreasing. The compensation architectures that have been devised to address this issue tend to be complicated and defy a tractable intuitive analysis and several works have been dedicated to deriving intuitive expressions for three-stage OTA transfer functions once their compensation structure is given [16,17,18,19,20] These works allow engineers to quickly derive expressions for pole and zero frequencies to be used in hand analysis and design but do not comment on the relative merits of different compensation architectures.

A Control Perspective on Multistage Amplifier Design
Challenges in Multistage Amplifier Compensation
Inadequacy of the Phase Margin as a Stability Criterion
Difficulty of Estimating the Gain and Phase Margins
Alternative Design Approach
Architecture Selection
Proposed FoM for Architecture Selection
Classification of Multistage Amplifier Architectures
A3 ω0i p
OTAs with Miller-Compensated Inner Amplifier
OTAs with Uncompensated Inner Amplifier
Other Compensation Architectures
Circuit-Level Considerations
Cascode Compensation
Slew Rate Enhancers
Confirmation of Results through Transistor Simulations
Schematic Diagrams
Selection of Circuit Parameters
Simulation Results
Conclusions

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