Abstract
This paper proposes an analytical model for the optimized design of a switched-capacitor programmable voltage reference (SC-PVR). This PVR topology guarantees a straightforward design, easy portability across different technology nodes, and does not require any special technology option. The developed model allows the study of the trade-offs and the a priori evaluation of the system performance. The circuit design optimization is carried out with MATLAB, and it permits SC-PVR to achieve current consumptions of few tens of nanoampere, with a voltage ripple specification of 500 μV. An SC-PVR has been designed in 65-nm CMOS technology, with a sizing extracted by the model optimization. Transistor-level simulation results are aligned with MATLAB results and confirm that the investigated architecture is suitable for ultra low-power applications.
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