Transient Voltage Suppressor Devices Research Articles

Transient Analysis of ESD Protection Circuits for High-Speed ICs

Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliability problems in electronic devices. Transient voltage suppressor (TVS) diodes are installed on high-speed I/O traces to improve system-level ESD protection. To protect the circuit, the majority of ESD current must flow into the external TVS diode rather than into the IC, but due to turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior, the TVS diode may not snap back when needed and the IC's internal protection may take most of the current. These race conditions between the internal and external ESD protection circuits were investigated for a universal serial bus(USB) interface board. The transient turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior of the on-chip and off-chip protection circuitry was characterized by measurements and by system efficient ESD design (SEED) simulations. The effect of transmission line pulses (TLP pulses) and power supply voltages of different sizes on the response of the protection circuitry were monitored and compared with SEED simulations. SEED models showed good agreement with measurements and were used to study the impact of passive components added to a high-speed trace or within the IC package on the ESD protection response. Results show the importance of properly accounting for the parasitic resistance and inductance between the on-chip diode and off-chip TVS diode, as well as the length of the transmission line when choosing the external TVS device. Results also show that testing must be performed using mid-level events to account for possible problems due to race conditions.

Design and Optimization of High-Failure-Current Dual-Direction SCR for Industrial-Level ESD Protection

In an industrial-grade bus, transient voltage suppressor (TVS) devices that need to withstand inrush currents ensure electrostatic discharge (ESD) reliability of the core chip. This article designs four types of dual-direction silicon-controlled rectifier (DDSCR) device structures based on the 0.5-μm CMOS process. The ESD performance of the TVS device is predicted and verified based on the basic principles of the device, two-dimensional device simulation, and transmission line pulse test results. Four DDSCR structures are embedded with floating N+ to adjust the device's holding voltage window. The results show that the current release capacity of DDSCR_1 is 81.93 mA/μm. The current release capability of DDSCR_2, which has a double-dummy-gate structure, is 82.37 mA/μm. The current release capability of DDSCR_3 of the gate-controlled structure is 86.68 mA/μm. The current release capability of DDSCR_4 of the double-dummy-gate structure and the gate-controlled structure is 86.25 mA/μm. Furthermore, the effect of the size of these devices on the ESD characteristics was studied. The on-resistance of the device structure is calculated by the curve-fitting method. The influence of the dummy gate structure and the gate-controlled structure on the ESD characteristics is analyzed. Finally, the optimal device size to meet the window is found.

System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips

This paper proposed a co-packaged methodology using transient voltage suppressor (TVS) chips and a controller area network (CAN) bus transceiver to ensure IEC 61000-4-2 system-level ESD protection. The design methodology is verified in a high-voltage silicon-on-insulator process for CAN transceiver chip and an 0.8- ${\mu }\text{m}$ bipolar process for TVS chips. The ${I}$ – ${V}$ curves of the TVS and CAN transceiver chip are evaluated by the transmission line pulsing system with the pulse width of 100 ns. The breakdown voltage of the bi-directional TVS chips and CAN transceiver chip are higher than ±80 V compared with the ±70 V fault voltage tolerance requirement. The clamping voltage of the TVS device is lower than ±130 V to discharge ESD current before the CAN transceiver chip breakdown for effective ESD protection. The design target of parasitic inductance by bonding wires is calculated to meet the clamping voltage requirement. The CAN bus transceiver IC with TVS chips co-packaged has been evaluated to pass the IEC61000-4-2 contact ±15-kV stress without any hardware damages and latch-up issues.

Transient voltage suppressor based on diode-triggered low-voltage silicon controlled rectifier

Transient voltage suppressor (TVS) has been widely used for electronic system ESD protection. A good TVS is usually costive as it needs some special processes and with extra masking layers for fabrication. A novel TVS design based on the standard CMOS process will be much attractive. This work proposes a new TVS device using a CMOS compatible diode-triggered silicon controlled rectifier (DLVTSCR) as the core device. Due to the available of multiple trigger mechanisms and the dual current paths for bypassing the ESD current, the newly proposed device is able to sink an ESD current of over 10 A. In addition, the holding voltage is promoted up to 6.83 V and the trigger voltage is lowered down to 10.8 V which is well suit for most portable device applications.

Effects of Electrostatic Discharge Stress on Electrical Properties of Bidirectional TVS Zener Diode with Abrupt Junctions

A bidirectional transient voltage suppressor (TVS) Zener diode was fabricated with abrupt junctions using the low-temperature epitaxy process. The effects of various electrostatic discharge (ESD) stresses on the electrical properties are demonstrated, such as the current­voltage (I­V) and 1/f noise power spectral density (PSD). Very sharp and uniform bidirectional multi-junctions result in good symmetric I­V behavior over a wide range of operating temperatures of 300­450K. The differential resistance in the breakdown region is only 0.2 ³, and the reverse leakage current density is completely suppressed to 1.5 © 10 ¹4 A/m 2 . The thermal activation energy obtained from the Arrhenius plot is nearly equal to half the band gap of Si, indicating that the reverse leakage current is dominated by thermal generation at the depletion edges for the entire reverse bias regions. The manufacture bidirectional TVS devices exhibit excellent ESD robustness, regardless of the stress conditions of the human body model and electrical fast transient. However, a «4.5kV machine model and «13kV IEC61000-4-2 stresses led to severe damage of the epitaxially grown junction, resulting in rapid increases in both the reverse leakage current and 1/f noise PSD. [doi:10.2320/matertrans.M2013144]

Development of Transient Voltage Suppressor Device with Abrupt Junctions Embedded by Epitaxial Growth Technology

A new Zener transient voltage suppressor (TVS) consisting of abrupt junctions of epitaxial layers has been developed. Differential resistance in the breakdown region is obtained as low as 5Ω, and the reverse leakage current is substantially suppressed by one to two orders of magnitude compared to a conventional Zener diode. The reliability of the TVS is confirmed based on its maximum allowed reverse current level and the robustness of its electrostatic discharge endurance against ±8 kV of the human body model (HBM) at a wide range of operating temperatures (30°C to 180°C). This significant improvement is primarily attributed to the abrupt junction profile formed by low-temperature processes, followed by epitaxial growth technology prohibiting redistribution of dopant elements.

A quasi-analytical breakdown voltage model in four-layer punch-through TVS devices

A quasi-analytical model addressed to predict the breakdown voltage in four-layer transient voltage suppressor (TVS) diodes based on the punch-through effect is reported in this paper. For breakdown voltage in excess of 1 V, a closed form expression is derived. In addition, the three-layer TVS diode can also be described with the developed model. Finally, results obtained from the model are in good agreement with simulation and experimental data.

Lateral punch-through TVS devices for on-chip protection in low-voltage applications

A novel lateral punch-through TVS (Transient Voltage Suppressor) structure addressed to on-chip protection in very low voltage applications is reported in this paper. Different lateral TVS structures have been studied in order to optimize the electrical performances related with the surge protection capability. Lateral TVS structures with a four-layer doping profile exhibit the best electrical performances, as in the case of vertical TVS devices. The dependence of the basic electrical characteristics on the technological and geometrical parameters is also analysed. Finally, the electrical performances of lateral TVS structures are compared with those of vertical punch-through TVS devices and conventional Zener diodes, being the leakage current level reduced two orders of magnitude in the case of the lateral architecture. Lateral TVS structures exhibits similar performance than vertical counterparts with the advantage of easiest on-chip integration.

Punchthrough diode as the transient voltage suppressor for low-voltage electronics

Protection devices for future low-voltage electronics are needed. Performances of a new punchthrough transient voltage suppressor (TVS) are analyzed with two-dimensional device simulation. Compared with the available low-voltage TVS constructed with a Zener diode, the punchthrough diode shows far superior leakage current and capacitance. These punchthrough TVS devices are satisfactory for applications not only at 3 V but even at 1 V.