Transient Fault Rates Research Articles

Power-Efficient and Aging-Aware Primary/Backup Technique for Heterogeneous Embedded Systems

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic Voltage and Frequency Scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore platforms have received much attention due to their ability to make a trade-off between power consumption and performance. Still, it is more complicated to map and schedule tasks in a heterogeneous multicore system. In this paper, for the first time, we propose a power management method for a heterogeneous multicore system that reduces power consumption and tolerates both transient and permanent faults through primary/backup technique while considering core-level power constraint, real-time constraint, and aging effect. Experimental evaluations demonstrate the efficiency of our proposed method in terms of reducing power consumption compared to the state-of-the-art schemes, together with guaranteeing reliability and considering the aging effect.

Energy management of fault-tolerant real-time embedded systems through switching-activity-based techniques

Energy management and fault tolerance are essential aspects in designing most real-time embedded systems, and dynamic voltage and frequency scaling (DVFS) is a fundamental approach in energy management. Using DVFS can lead to a considerable decrease in the system's reliability as the rate of transient faults increases due to low voltage and frequency. This study focuses on finding and implementing methods that address the following three issues in hard real-time embedded systems: energy consumption, fault tolerance, and time limitations. Switching activity depends on the nature of tasks. Since the switching activity is task-specific, the energy consumption of a task can be significantly greater than that of other tasks. As far as we know, previous studies on the power management of fault-tolerant real-time systems have not considered switching activity, so the impact of this factor is considered in this study. Multiple heuristic methods are proposed based on the switching activity factor to minimize energy consumption while sustaining the system's original reliability. In the proposed methods, the order of task execution is determined based on task switching activities. The methods are developed for both periodic and frame-based task models. The results show that the proposed methods can decrease the energy consumption by 12.7 %∼35.5 % for the periodic task model and 17.4 %∼45.2 % for the frame-based task model while preserving the system's reliability.

M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures

Coarse-grained reconfigurable architectures (CGRAs) can provide both energy efficiency and performance for embedded systems, and thus they are increasingly deployed in the areas of aerospace, automotive engineering, and security where reliability is also a main criterion. However, the state-of-the-art fault-tolerant strategies for CGRAs apply either temporal or spatial scheme, including redundancy, periodic detection, workload balancing, and reconfiguration, failing to exploit the feature of dynamic and partial reconfiguration of CGRAs. Also, vulnerable judging circuits and inflexible mode shifting bottleneck the reliability design of fault-tolerant CGRAs. This paper proposes a novel multi-mode fault-tolerant framework for CGRAs, which combines spatial-redundant data-paths with temporal-redundant voters and thus reduces the vulnerable judging circuits while balancing the performance and reliability. This framework can also enable a changing reliability level at runtime via an online configuration transformation method based on pre-compiled patterns. Within the proposed framework, we systematically searched the design space spanning various combinations of the mainstream schemes with a Markov process model to compare the effectiveness and accordingly selected five points as available modes in our design after comprehensive consideration of fault tolerance and time overhead on CGRA. The framework is comprehensively evaluated on a cycle-accurate CGRA simulator, considering both permanent and transient faults. The experimental results show that the fault coverage rate of single transient faults or permanent faults has increased from 71.74% to 93.84%, which means the fault tolerance of the system has been increased by 31.03% compared with the state-of-the-art methods. There is also a great improvement in mean-time-to-failure (MTTF) and reconfiguration latency over baseline designs.

A Minimizing Energy Consumption Scheme for Real-Time Embedded System Based on Metaheuristic Optimization

With the widespread application of real-time embedded systems, the contradiction between the energy consumption requirements of modern processors and the limited battery capacity becomes more obvious. Dynamic voltage scaling (DVS) has been proven to be one of the most effective technologies for energy management. However, recent studies have shown that the use of DVS leads to a significant increase in the transient fault rate of processors as the characteristic size of logic gates (or transistors) gets smaller and smaller. In this paper, we consider the problem of assigning processing frequencies to a group of periodic real-time tasks so as to minimize the overall energy consumption under the constraints of time and reliability. Firstly, under the DVS, we take the reliability of the embedded systems into consideration through the regularization terms and present the energy consumption optimization model based on the meta-heuristic algorithms. Secondly, a novel algorithm for adaptive differential whale swarm optimization (ADWOA) is proposed according to the optimization requirements. Finally, the optimized data are saved on the chain through the storable feature of the blockchain for the necessary queries. It is worth noting that the on-chain data contains the intrinsic characteristics of the embedded system, which may give rise to the disclosure of processor privacy. Therefore, we come up with the differential privacy on-chain creating algorithm (DPCA) to protect the privacy of data on the chain. Experimental results show that ADWOA can minimize the energy consumption in real-time embedded system on the premise of ensuring system reliability and privacy.

Reliability aware green workflow scheduling using \u03b5-fuzzy dominance in cloud

The enormous energy consumed by cloud data centers (CDCs) increases the carbon footprints, operational cost and decreases the system reliability, so it becomes a great challenge for CDCs providers. Dynamic voltage and frequency scaling (DVFS) is an efficient approach for energy efficiency, which reduces the operating frequency, and supply voltage of the processor during the task’s execution. Recent research shows that scaling of the supply voltage and operating frequency has negative impact on the system’s reliability as it increases transient fault rate of the resources. Thus, the system’s reliability and the energy consumption are two prime concerns in a cloud computing environment that requires attention. Most workflow scheduling algorithms in literature do not consider energy and reliability simultaneously. In this paper, we proposed the ε-fuzzy dominance based reliable green workflow scheduling (FDRGS) algorithm, which optimizes the application’s reliability and energy consumption simultaneously using the ε-fuzzy dominance mechanism. The simulation results obtained using fast Fourier transform (FFT) and gaussian elimination (GE) task graphs manifest that our scheduling algorithm is more efficient in optimizing energy consumption and lifetime system’s reliability jointly than several widely used algorithms. The proposed algorithm will help scientists and engineers for further insight into future research in the area of cloud.

Programming-level and redundancy-free method for enhancing software reliability against transient errors in hardware

Software play remarkable roles in different critical applications. On the other hand, due to the shrinking of transistor size and reduction in supply voltage, radiation-induced transient errors (soft errors) have become an important source of computer systems failure. As the rate of transient hardware faults increases, researchers have investigated software techniques to control these faults. Performance overhead is the main drawback of software-implemented methods like recovery blocks that use technical redundancy. Enhancing the software reliability against soft errors by utilizing inherently error masking (invulnerable) programming structures is the main goal of this study. During the programming phase and at the source code level, programmers can select different storage classes such as automatic, global, static and register for the data into their program without paying attention to their inherent reliability. In this study, the inherent effects of these storage classes on the program reliability are investigated. Extensive series of profiling and fault-injection experiments were performed on the set of benchmark programs implemented with different storage classes. Regarding the results of experiments, we find that the programs implemented with automatic storage classes have inherently higher reliability than the programs with static and register storage classes without performance overhead. This finding enables the programmers to develop highly reliable programs without technical redundancy and performance overhead.

Energy Efficient and Reliability Aware Workflow Task Scheduling in Cloud Environment

With the rising demand for cloud services, the high energy consumption of cloud data centers is a significant problem that needs to be handled. The Dynamic Voltage and Frequency Scaling approach has been identified as one of the efficient techniques to conserve energy, particularly while scheduling real-world scientific workflows. Moreover, scientific workflows demand high-availability of the system. The computational systems in the cloud data centers are not failure-free and further frequency scaling impacts negatively on the reliability of the system by increasing the transient fault rate. A trade-off is required between energy conservation and the reliability of the computational machine. In this paper, we propose an energy-efficient and reliability aware workflow task scheduling in a cloud environment (EERS) algorithm, which conserves energy and maximizes the system reliability. The EERS comprises five sub-algorithms. First, we apply a task rank calculation algorithm to preserve the task dependencies. Second, a task clustering algorithm to reduce the communication cost which reduces energy consumption. The third is the sub-target time distribution algorithm to define the sub_makespan for each task. Further, we propose a cluster-VM mapping algorithm that reduces energy and maximizes system reliability and finally, a slack algorithm to reclaim slack associated with the non-critical tasks. The performance of the EERS evaluated on the WorkflowSim simulator using two real-world scientific workloads CyberShake and Montage. The results indicate that it surpasses the related existing approaches.

Multi-objective redundancy hardening with optimal task mapping for independent tasks on multi-cores

The rate of transient faults has increased significantly as the technology scales up. The tolerance of transient faults has become an important issue in the system design. Dual modular redundancy (DMR) and triple modular redundancy (TMR) are two commonly used techniques that can achieve fault detection and masking through executing redundant tasks. As DMR and TMR have different time and cost overheads, we must carefully determine which one should be used for each task (i.e., task hardening) to achieve the optimal system design. Furthermore, for multi-core systems, the system-level design includes the allocation of cores for the tasks (i.e., task mapping) as well. This paper aims at task hardening and mapping simultaneously for independent tasks on multi-cores with heterogeneous performances, in order to minimize the maximum completion time of all tasks (i.e., makespan). We demonstrate that once task hardening is given, task mapping of independent tasks can be achieved by employing min–max-weight perfect matching with a polynomial time complexity. Besides, as there is a trade-off between cost and time performance, we propose a multi-objective memetic algorithm (MOMA)-based task hardening method to obtain a set of solutions with different numbers of cores (i.e., costs), so the designer can choose different solutions according to different requirements. The key idea of the MOMA is to incorporate problem-specific knowledge into the global search of evolutionary algorithms. Our experimental studies have demonstrated the effectiveness of the proposed method and have shown that by combining the results of MOMA and MOEA we can provide a designer with a highly accurate set of solutions within a reasonable amount of time.

On Reliability Management of Energy-Aware Real-Time Systems Through Task Replication

On emerging multicore systems, task replication is a powerful way to achieve high reliability targets. In this paper, we consider the problem of achieving a given reliability target for a set of periodic real-time tasks running on a multicore system with minimum energy consumption. Our framework explicitly takes into account the coverage factor of the fault detection techniques and the negative impact of Dynamic Voltage Scaling (DVS) on the rate of transient faults leading to soft errors. We characterize the subtle interplay between the processing frequency, replication level, reliability, fault coverage, and energy consumption on DVS-enabled multicore systems. We first develop static solutions and then propose dynamic adaptation schemes in order to reduce the concurrent execution of the replicas of a given task and to take advantage of early completions. Our simulation results indicate that through our algorithms, a very broad spectrum of reliability targets can be achieved with minimum energy consumption thanks to the judicious task replication and frequency assignment.

NBTI-Aware Transient Fault Rate Analysis Method for Logic Circuit Based on Probability Voltage Transfer Characteristics

The reliability of Very Large Scale Integration (VLSI) circuits has become increasingly susceptible to transient faults induced by environmental noise with the scaling of technology. Some commonly used fault tolerance strategies require statistical methods to accurately estimate the fault rate in different parts of the logic circuit, and Monte Carlo (MC) simulation is often applied to complete this task. However, the MC method suffers from impractical computation costs due to the size of the circuits. Furthermore, circuit aging effects, such as negative bias temperature instability (NBTI), will change the characteristics of the circuit during its lifetime, leading to a change in the circuit’s noise margin. This change will increase the complexity of transient fault rate estimation tasks. In this paper, an NBTI-aware statistical analysis method based on probability voltage transfer characteristics is proposed for combinational logic circuit. This method can acquire accurate fault rates using a discrete probability density function approximation process, thus resolving the computation cost problem of the MC method. The proposed method can also consider aging effects and analyze statistical changes in the fault rates. Experimental results demonstrate that, compared to the MC simulation, our method can achieve computation times that are two orders of magnitude shorter while maintaining an error rate less than 9%.

An Adaptive Approach to Discriminate the Persistence of Faults in Wireless Sensor Networks

This paper presents a parametric fault detection algorithm which can discriminate the persistence (permanent, intermittent, and transient) of faults in wireless sensor networks. The main characteristics of these faults are the amount the fault appears. We adopt this state-holding time to discriminate transient from intermittent faults. Neighbor-coordination-based approach is adopted, where faulty sensor nodes are detected based on comparisons between neighboring nodes and dissemination of the decision made at each node. Simulation results demonstrate the robustness of the work at varying transient fault rate.

Adaptive fault-tolerant DVFS with dynamic online AVF prediction

Advances in silicon technology and shrinking the feature size to nanometer levels make random variations and low reliability of nano-devices the most important concern for fault-tolerant design. Design of reliable and fault-tolerant embedded processors is mostly based on developing techniques that compensate reliability shortcomings by adding hardware or software redundancy. The recently-proposed redundancy adding techniques are generally applied uniformly to all parts of a system and lead to heavy overheads and inefficiencies in terms of performance, power, and area. Efficient employment of non-uniform redundancy becomes possible when a quantitative analysis of a system behavior while encountering transient faults is provided. In this work, we present a quantitative analysis of the behavior of an embedded processor regarding transient faults and propose a new approach that accurately predicts the architecture vulnerability factor (AVF) in real-time. Another critical concern in design of new-silicon processors is power consumption issue. Dynamic voltage and frequency scaling (DVFS) is an effective method for controlling both energy consumption and performance of a system. Since rate of radiation-induced transient faults depends on operating frequency and supply voltage, DVFS techniques are recently shown to have compromising effects on electronic system reliability. Therefore, ignoring the effects of voltage scaling on fault rate could considerably degrade the system reliability. Here, by exploiting the proposed online AVF prediction methodology and based on analytic derivation, we propose a reliability-aware adaptive dynamic voltage and frequency scaling (DVFS) approach in case study of Multi-Processor System on Chip (MPSoC) with Multiple Clock Domain (MCD) pipeline architectures in which the frequency and voltage are scaled by simultaneously considering all three of power consumption, reliability, and performance. Comparing to the traditional methods of reliability-aware DVFS systems, the proposed reliability-aware DVFS method yields 50% better power saving at the same reliability level.

Quasi-static fault-tolerant scheduling schemes for energy-efficient hard real-time systems

This paper investigates fault tolerance and dynamic voltage scaling (DVS) in hard real-time systems. The authors present quasi-static task scheduling algorithms that consist of offline components and online components. The offline components are designed the way they enable the online components to achieve energy savings by using the dynamic slack due to variations in task execution times and uncertainties in fault occurrences. The proposed schemes utilize a fault model that considers the effects of voltage scaling on transient fault rate. Simulation results based on real-life task sets and processor data sheets show that the proposed scheduling schemes achieve energy savings of up to 50% over the state-of-art low-energy offline scheduling techniques and incur negligible runtime overheads. A hard real-time real-life test bed has been developed allowing the validation of the proposed algorithms.

Reliability-aware dynamic energy management in dependable embedded real-time systems

Recent studies show that voltage scaling, which is an efficient energy management technique, has a direct and negative effect on system reliability because of the increased rate of transient faults (e.g., those induced by cosmic particles). In this article, we propose energy management schemes that explicitly take system reliability into consideration. The proposed reliability-aware energy management schemes dynamically schedule recoveries for tasks to be scaled down to recuperate the reliability loss due to energy management. Based on the amount of available slack, the application size, and the fault rate changes, we analyze when it is profitable to reclaim the slack for energy savings without sacrificing system reliability. Checkpoint technique is further explored to efficiently use the slack. Analytical and simulation results show that the proposed schemes can achieve comparable energy savings as ordinary energy management schemes (which are reliability-ignorant) while preserving system reliability. The ordinary energy management schemes that ignore the effects of voltage scaling on fault rate changes could lead to drastically decreased system reliability.

Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level

The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affected by transient faults is the interconnection network of chip multiprocessors (CMPs). To deal efficiently with these faults and differently from other authors, we propose to use fault-tolerant cache coherence protocols that ensure the correct execution of programs when not all messages are correctly delivered. We describe the extensions made to a directory-based cache coherence protocol to provide fault tolerance and provide a modified set of token counting rules which are useful to design fault-tolerant token-based cache coherence protocols. We compare the directory-based fault-tolerant protocol with a token-based fault-tolerant one. We also show how to adjust the fault tolerance parameters to achieve the desired level of fault tolerance and measure the overhead achieved to be able to support very high fault rates. Simulation results using a set of scientific, multimedia, and commercial applications show that the fault tolerance measures have virtually no impact on execution time with respect to a non-fault-tolerant protocol. Additionally, our protocols can support very high rates of transient faults at the cost of slightly increased network traffic.

Logic Self Repair Based on Regular Building Blocks

The scalability of CMOS technology is apparently approaching physical limits. In particular, technology forecasts expect higher rates of permanent and transient faults, which make fault tolerant design and, eventually, built-in self repair (BISR) capabilities a necessity. While BISR works reasonably in regular structures such as memory blocks, BISR for random logic is by far an unsolved problem. This paper introduces a novel systematic approach towards logic BISR and gives some indications for cost and limitations.

Is Asynchronous Logic More Robust Than Synchronous Logic?

With clock rates beyond 1 GHz, the model of a system wide synchronous clock is becoming difficult to maintain; therefore, asynchronous design styles are increasingly receiving attention. While the traditional synchronous design style is well-proven and backed up by a rich field experience, comparatively little is known about the properties of asynchronous circuits in practical application. In the face of increased transient fault rates, robustness is a crucial property, and from a conceptual view, the so-called ldquodelay-insensitiverdquo asynchronous design approaches promise to be more robust than synchronous ones, since their operation does not depend on tight timing margins, and data are two-rail coded. A practical assessment of asynchronous designs in fault-injection (FI) studies, however, can rarely be found, and there is a lack of adequate methods and tools in this particular domain. Therefore, the objective of this work is 1) to provide a common approach for efficient and accurate FI in synchronous and in asynchronous designs, and 2) to experimentally compare the robustness of both synchronous and asynchronous designs. To this end, a synchronous 16-bit processor as well as its asynchronous (delay insensitive) equivalent are subjected to signal flips and delay faults. The results of over 489 million experiments are summarized and discussed, and a detailed discussion on the specific properties of the chosen asynchronous design style is given.

A Probabilistic LDPC-Coded Fault Compensation Technique for Reliable Nanoscale Computing

A method is proposed for computing with unreliable nanoscale devices that have a high rate of transient errors. Errors are corrected using a probabilistic circuit in which device noise is leveraged as a computational asset. Example designs that achieve a low output bit error probability are presented. The effect of permanent defects is also evaluated, and transient device noise is found to be beneficial for correcting hard defects for defect rates of as high as 0.1% and transient fault rates above 1%. When compared with existing fault-tolerant methods, the sample design requires considerably fewer redundant gates to achieve reliable operation. These results predict that some degree of engineered randomness may prove to be a useful signal-processing feature in future nanoelectronic systems.

Fault-tolerant sub-lithographic design with rollback recovery

Shrinking feature sizes and energy levels coupled with high clock rates and decreasingnode capacitance lead us into a regime where transient errors in logic cannot beignored. Consequently, several recent studies have focused on feed-forward spatialredundancy techniques to combat these high transient fault rates. To complementthese studies, we analyze fine-grained rollback techniques and show that theycan offer lower spatial redundancy factors with no significant impact on systemperformance for fault rates up to one fault per device per ten million cycles of operation(Pf = 10−7) insystems with 1012 susceptible devices. Further, we concretely demonstrate these claims on nanowire-basedprogrammable logic arrays. Despite expensive rollback buffers and general-purpose,conservative analysis, we show the area overhead factor of our technique is roughly an orderof magnitude lower than a gate level feed-forward redundancy scheme.

Configurable isolation

High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redundant hardware for error detection and continued uptime in the event of a failure. Chip multiprocessors with an abundance of identical resources like cores, cache and interconnection networks would appear to be ideal building blocks for implementing high availability solutions on chip. However, doing so poses significant challenges with respect to error containment and faulty component replacement. Increasing silicon and transient fault rates with future technology scaling exacerbate the problem. This paper proposes a novel, cost-effective, architecture for high availability systems built from future multi-core processors. We propose a new chip multiprocessor architecture that provides configurable isolation for fault containment and component retirement, based upon cost-effective modifications to commodity designs. The design is evaluated for a state-of-the-art industrial fault model and the proposed architecture is shown to provide effective fault isolation and graceful degradation even when the failure rate is high.