NBTI-Aware Transient Fault Rate Analysis Method for Logic Circuit Based on Probability Voltage Transfer Characteristics

Zhiming Yang,Xiyuan Peng,Yang Yu,Junbao Li

doi:10.3390/a9010009

Abstract

The reliability of Very Large Scale Integration (VLSI) circuits has become increasingly susceptible to transient faults induced by environmental noise with the scaling of technology. Some commonly used fault tolerance strategies require statistical methods to accurately estimate the fault rate in different parts of the logic circuit, and Monte Carlo (MC) simulation is often applied to complete this task. However, the MC method suffers from impractical computation costs due to the size of the circuits. Furthermore, circuit aging effects, such as negative bias temperature instability (NBTI), will change the characteristics of the circuit during its lifetime, leading to a change in the circuit’s noise margin. This change will increase the complexity of transient fault rate estimation tasks. In this paper, an NBTI-aware statistical analysis method based on probability voltage transfer characteristics is proposed for combinational logic circuit. This method can acquire accurate fault rates using a discrete probability density function approximation process, thus resolving the computation cost problem of the MC method. The proposed method can also consider aging effects and analyze statistical changes in the fault rates. Experimental results demonstrate that, compared to the MC simulation, our method can achieve computation times that are two orders of magnitude shorter while maintaining an error rate less than 9%.

Highlights

Reliability issues have become a vital concern for Very Large Scale Integration (VLSI) design due to the continued scaling of VLSI technology and supply voltage
The density of memory circuits is much higher than logic circuits, which makes the memory circuits contain the largest number and density of bits susceptible to transient fault
We propose an negative bias temperature instability (NBTI)-aware statistical analysis method to address transient fault rate estimation for combination logic circuit that considers both environmental noise and the NBTI

Summary

Introduction

Reliability issues have become a vital concern for Very Large Scale Integration (VLSI) design due to the continued scaling of VLSI technology and supply voltage. Among these reliability issues, transient faults caused by environmental effects, such as electrical noise, particle strikes, and electromagnetic coupling, are primary failure mechanisms [1]. The three masking factors affect the propagation of a transient fault through combinational circuit, which include logical masking, electrical masking and latching-window masking. In the last decade, supply voltage continues to diminish in value with current scaling trends, causing a decrease in the impact of these masking factors on logic circuits [3,4].

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Conclusion