Transient Dual Interface Method Research Articles

Understanding Inherent Implication of Thermal Resistance in Double-Side Cooling Module

The double-side cooling (DSC) packaging becomes more and more popular with the great demands of high power and fast speed, especially for silicon carbide metal oxide semiconductor field effect transistors. Measurements and modeling of thermal resistance are critical for thermal management of DSC module. However, the thermal resistance of DSC module is still unclear due to the asymmetric dual thermal paths. In this article, a clear understanding of thermal resistance of DSC module measured by transient dual-interface method (TDIM) is explained. The thermal impedance of DSC module is analyzed through time- and frequency-domain response of the DSC thermal model. The cooling conditions in TDIM have no influence on the measured thermal resistance of DSC module. The measured thermal resistance from junction to top case (or bottom case) is half of the actual value. The important conclusions are verified by transient simulations and experiments. Based on the results, a new definition of thermal resistance of DSC module is proposed for exact evaluation of thermal resistance and reliability.

Transient thermal measurement on nano-metallic sintered die-attach joints using a thermal test chip

The rapid development of power electronics has challenged the thermal integrity of semiconductor packaging. Further developments in this domain can be supported significantly by utilizing fast and flexible thermal characteristic evaluation. This study employs the transient dual interface method (TDIM) to characterize and compare the thermal resistance of Ag- and Cu-sintered die-attach joints using an in-house developed thermal test chip (TTC). The proposed TTC with 82.5% active area achieves a temperature sensitivity of 12 Ω/K and maximum power of 360 W per cell, which are 50% and 44% higher than the state-of-the-art, respectively. The uniformity of the temperature distribution (1 °C at 68 W) is verified by infrared thermography. The cost-effective manufacturing process allows the design to be applied to any substrate, such as SiC or GaN. Ag and Cu sintering is performed to bond the TTC on a Cu substrate, and the junction-to-case thermal resistance of the sintered structures is extracted. The lowest junction-to-case thermal resistance of 0.144 K/W is measured for the device sintered using Ag paste. Meanwhile, the Cu sintered structure exhibits a comparable value of 0.158 K/W. The proposed TTC in combination with TDIM accelerates the introduction of novel and cost-effective materials such as Cu.

Investigations on High-Power LEDs and Solder Interconnects in Automotive Application: Part I—Initial Characterization

Thermo-mechanical reliability is one major issue in solid-state lighting. Mismatches in the coefficients of thermal expansion (CTE) between high-power LED packages and substrates paired with temperature changes induce mechanical stress. This leads to a thermal degradation of LED modules by crack formation in the solder interconnect and/or delamination in the substrate, which in turn increases junction temperature and thus decreases light output and reduces lifetime. To investigate degradation and understand influence of LED package design and solder material, a reliability study with a total of 1800 samples − segmented in nine LED types and five solder pastes − is performed. First of all, in this paper a state-of-the-art review of high-power LED packages is performed by analyzing and categorizing the packaging technologies. Second, the quality inspection after assembly is realized by transient thermal analysis (TTA), scanning acoustic microscopy (SAM) and X-ray. For TTA, a new method is introduced to separate the thermal resistance of the LED package from solder interconnect and substrate by applying the transient dual interface method (TDI) on samples with different solder interconnect void ratios. Further measurement effort is not required. The datasheet values for thermal resistance are verified and the different LED package types are benchmarked. The void ratio of the solder interconnects is determined by X-ray inspection combined with an algorithm to suppress disruptive internal LED package structures. TTA and TDI revealed that initial thermal performance is independent of solder paste type and that voiding is more critical to smaller LED packages. In addition, lower silver proportion in the paste is found to increase voiding. SAM is less sensitive for initial void detection than X-ray, but it’s applied to monitor crack propagation while aging in combination with TTA. The results of the reliability study, i.e., the crack growth under temperature shock test for the different SAC solders, will be presented in a second independent paper.

Effect of Shell Temperature on Thermal Resistance and Junction Temperature for Power Diode

Accurate measurement of junction temperature can avoid thermal failure of diode. During aging test, junction temperature should be indirectly calculated by testing its thermal resistance. In this paper, junction-to-case thermal resistance (Rthjc) of XX diode is tested by T3ster based on transient dual interface method. Its Rthjc is about 1.23K/W at 25°C and contains PN junction thermal resistance, metal shell thermal resistance and Sn-based solder thermal resistance, respectively. These three types of thermal resistance decrease in order. Effect of shell temperature on junction temperature and Rthjc is then discussed. As shell temperature increases, temperature variation of PN junction before and after heating and corresponding thermal resistance Rthjc both increase.

(Invited) How to Achieve Low Thermal Resistance and High Electrothermal Ruggedness in Ga2O3 Devices?

Ultra-wide-bandgap semiconductor gallium oxide (Ga2O3) has been promoted for years as a promising candidate for power electronics and RF applications, due to its high critical electrical field, controllable n-type doping, and the availability of large-diameter wafers by the melt growth. However, a fundamental limitation of Ga2O3 is its low thermal conductivity (k T = 0.1-0.3 Wcm-1K-1), which is about 1/6 of the k T of Si, 1/10 of GaN, and 1/20 of SiC. The resulting high thermal resistance of Ga2O3 chip has brought serious concerns regarding the current and power scalability of Ga2O3 devices and their electrothermal ruggedness. As a result, questions have persisted on the true viability of Ga2O3 devices in industrial power and RF applications.Despite some simulation and modeling works on the Ga2O3 thermal management, there has been no experimental report on the packaging and thermal management of large-area Ga2O3 devices. The lack of these data makes it difficult to compare Ga2O3 with commercial device technologies (e.g., Si, SiC, GaN) and evaluate the application space of Ga2O3 devices. Some recent works characterized the channel (or junction) temperatures in Ga2O3 devices, but all of these devices have small areas with a current much lower than 1 Amp, and none of these devices are packaged.This work presents the first experimental demonstration of large-area Ga2O3 devices and their thermal management through device-package co-optimization. Vertical Ga2O3 Schottky barrier diodes (SBDs) with a 3×3 mm2 Schottky contact area were fabricated with an on/off ratio over 1010, a forward current over 20 A, and a reverse breakdown voltage over 600 V. These large-area Ga2O3 SBDs were packaged in the bottom-side-cooling and double-side-cooling configurations using the nanosilver sintering as the die attach and the silver plate as the thermal pad.Surge current ruggedness is an essential ruggedness metric listed in any power diode’s datasheet and the most important indicator of a device’s transient electrothermal ruggedness. It measures the device’s capability of temporarily sustaining a current much higher than the rated current. To evaluate the surge current ruggedness of packaged Ga2O3 devices, a surge-current test circuit was prototyped to produce a 10-ms-wide half-sinusoidal current waveform based on the JEDEC standard. The surge-current tests revealed a critical surge current of 37.5 A for the single-side-packaged Ga2O3 SBD and 68 A for the double-side-packaged Ga2O3 SBD. The ratio between the peak surge current and the rated current of the double-side-packaged Ga2O3 SBD was found to be superior to that of similarly-rated commercial SBDs.The key enabling mechanisms for this superior-to-SiC surge current capability are two-fold: first, the fabricated Ga2O3 SBD shows a smaller temperature dependence of on-resistance as compared to the SiC SBDs, which strongly reduces the thermal runaway; second, the double-side-packaging allows the heat to be extracted directly from the Schottky junction without the need for going through the low-k T bulk Ga2O3 chip.To further evaluate the steady-state thermal performance of these Ga2O3 SBDs, the junction-to-case thermal resistance (R θJC) of a double-side-packaged Ga2O3 SBD was measured in the bottom-side- and junction-side-cooling configurations. The R θJC characterization is based on the transient dual interface method, i.e., JEDEC 51-14 standard. The R θJC of the junction- and bottom-cooled Ga2O3 SBD was measured to be 0.5 K/W and 1.43 K/W, respectively, with the former R θJC lower than that of similarly-rated commercial SiC SBDs. This low R θJC is attributable to the heat extraction directly from the Schottky junction instead of through the Ga2O3 chip.The higher surge current ruggedness and lower thermal resistance demonstrated in a large-area, packaged Ga2O3 SBD as compared to the similarly-rated SiC devices proves the viability of Ga2O3 devices for high-power applications. Note that no complex or costly process, such as substrate thinning and layer transfer, has been applied to our Ga2O3 chip. These results manifest that device-packaging co-optimization is an effective and low-cost approach for the thermal management of Ga2O3 devices.

Temperature Influence on the Accuracy of the Transient Dual Interface Method for the Junction-to-Case Thermal Resistance Measurement

The transient dual interface method (TDIM), proposed by the JEDEC 51-14 standard [1], determines the junction-to-case thermal resistance of power electronics with the separate point of two transient thermal impedance curves under different contact conditions. However, the influence of the junction temperature is not considered and this underestimates the actual value with earlier separation point. This phenomenon is presented first with experimental results at different junction temperatures. Electro-thermal finite element simulations and simulation with semiconductor physical behavior in the devices simulations are performed to explain the root reason. After that, the improved TDIM with the junction temperature compensation is proposed to improve the accuracy. The experimental results show that the improved TDIM improves the accuracy of about 9.5% for 600-V discrete IGBT devices.

Study on the Method to Measure the Junction-to-Case Thermal Resistance of Press-Pack IGBTs

Accurate measurement of the junction-to-case thermal resistance of press-pack insulated gate bipolar transistors (PP IGBTs) is a great challenge due to their special packaging style and working conditions. The traditional thermocouple and transient dual interface methods have been successfully applied to measure the junction-to-case thermal resistance of wire-bonded IGBT modules. In this paper, a single fast-recovery diode (FRD) chip submodule is fabricated to determine the best method to measure the junction-to-case thermal resistance of PP IGBTs. Therefore, both the traditional thermocouple method and the transient dual interface method were used to measure the junction-to-case thermal resistance of the collector-side cooling with the emitter-side adiabatic. The transient dual interface method, which does not require locating a thermocouple to measure the case temperature, is ideal for the PP IGBTs measurement based on the experimental results and theoretical verification. Most importantly, both bulk thermal resistance of specific layers and thermal contact resistance between multilayers in PP IGBTs can be obtained by transforming the transient thermal-impedance curve.

Study on the methods to measure the junction-to-case thermal resistance of IGBT modules and press pack IGBTs

The accurate measurement of the junction-to-case thermal resistance of Insulated Gate Bipolar Transistor (IGBT) devices is notably important for manufacturers to optimize the internal structure of packaging in order to improve its reliability and for users to take full advantage of the devices. The existing differences between IGBT modules and press pack IGBTs (PP IGBTs) not only in their packaging styles, but also in their working conditions may lead to some differences in the methods to measure their junction-to-case thermal resistance. In this paper, the junction-to-case thermal resistances of both IGBT modules and PP IGBTs have been measured using the traditional thermocouple method (steady-state method) and transient dual interface method (transient method). The applicability of these two methods for the measurement of junction-to-case thermal resistance of IGBT modules and PP IGBTs is summarized based on the experimental results. The steady-state method is suitable for the measurement of junction-to-case thermal resistance of IGBT modules, but not for PP IGBTs, because of the thermocouple inserted to measure the case temperature. The transient method is appropriate for the measurement of junction-to-case thermal resistance of not only IGBT modules, but also PP IGBTs, as a thermocouple is not required to measure the case temperature.

Transient dual interface measurement of junction-to-case thermal resistance in AlGaN/GaN HEMT utilizing an improved infrared microscope

The junction-to-case thermal resistance (RθJC) of a GaN/AlGaN HEMT is measured by Transient Dual Interface Method (TDIM). Different from other works about TDIM, an improved transient infrared microscope is used to measure the cooling curves, other than the traditional electrical method. Zth curves are used to determine the RθJC following the procedure of JESD51-14. The results demonstrate that the RθJC at 40W power dissipation are about 0.791K/W. In order to validate the method, measurements following MIL Std 833 have been done, and the results are consistent with the existing papers.

Thermal characterization of planar high temperature power module packages with sintered nanosilver interconnection

Many new innovations have emerged in the power electronics industry to aid in meeting the expanded market demand. In spite of that the interest in high temperature and high power applications has fueled new developments in wide bandgap semiconductor devices which are capable of operation above 200°C, silicon devices are still prevalent in the marketplace and offer significant power ratings at affordable prices. Researches have kept pushing the limit of the application temperature of silicon devices. The key to offering functional and reliable silicon packages that can endure higher temperatures is through innovative thermal management and packaging. Effective thermal management of packaged devices can be accomplished through materials selection, design or a combination of the two. In this paper, we outline a newly designed packaging structure and the fabrication process of a functional double-sided power module switching units utilizing LTJT sintered silver for each interface. The thermal characteristics of the power module were measured in various cooling scenarios utilizing thermal transient measurements, structure function analysis and the transient dual interface method (TDIM), techniques developed by Mentor Graphics. Significant improvement of thermal performance of the fabricated module was demonstrated. The resulting improvements in thermal resistance of the power module, thermal simulation model agreement and construction, and comparison of double sided thermal results to single sided conventions are discussed.

A novel flat polymer heat pipe with thermal via for cooling electronic devices

The efficiency and heat transfer characteristics of a newly designed flat polymer heat pipe that uses copper micro thermal via was investigated using a fabricated laboratory model to measure the amount of heat that could be removed from a given heat source (a heater or a light emitting diode (LED) module) under a range of different operating conditions. The heat pipe consists of a copper frame 1mm thick which is sandwiched between top and bottom sheets of FR4 polymer to form a vapor chamber. Copper meshes were used for the wick structure in the vapor chamber. The design also includes an array of thermal via, formed by 0.5mm holes drilled through the polymer, which are copper plated and filled with resin similar to the FR4 polymer. This novel design enhances heat conduction through the wall of the polymer heat pipe. A transient dual interface method (TDIM) was used to measure the thermal resistance of the LED module mounted on the flat heat pipe. Experimental results showed that use of the thermal via design reduced the lateral thermal resistance by 20–25%. The thermal resistance of the flat heat pipe was also affected by the filling ratio of working fluid and the tilt angle. When the flat heat pipe with thermal via was used as a mounting substrate with the LED module located in the center of the top surface, experimental results showed the thermal resistance of the substrate was reduced by 57%.

Development of a standard for transient measurement of junction-to-case thermal resistance

The paper summarizes the development of a standard method to measure the thermal resistance “junction-to-case”θJC of semiconductor devices with heat flow through a single path. Power switches or amplifiers are typical examples. θJC is a key performance metric to decide whether a device can be used in thermally critical applications. Hence an accurate and reproducible method to measure θJC is required. This is not easy, especially for low θJC, which is reflected by the fact that no JEDEC industry standard existed then to measure θJC. During the last 4years we have evaluated approaches and developed a new method called Transient Dual Interface (TDI) method. It uses two measurements of the thermal impedance Zth or more specific ZθJC(t) of the device with different cooling conditions at the interface of device case and a heat sink. To evaluate these measurements two methods are applied. Method 1 determines θJC directly from the separation of Zth-curves. θJC is the thermal impedance ZθJC(ts) at the time ts where the two ZθJC(t)-curves separate. Method 2 first calculates cumulative structure functions and uses their separation point to determine θJC. Both data evaluation methods complement each other, because method 1 is most accurate for low θJC in the range of 1K/W or below, while method 2 is more accurate for higher θJC>1K/W. The TDI method allows to measure θJC with higher accuracy and better reproducibility than the steady state method used in industrial practice up to now. The TDI method was published as JEDEC standard JESD51-14 in November 2010. Problems of the traditional steady state measurement and main steps of the development of the TDI method are discussed.

Thermal Transient Measurements on High Power LEDs with Different MCPCB Substrate

This study elucidates the significance of thermal transient measurement based on structure function evaluation particularly on high power LEDs. The metal core printed circuit boards (MCPCBs) were redesigned with reference to the product datasheet. Aluminium nitride was employed as the dielectric material of the MCPCBs and thermal performance of copper and aluminium substrate with different substrate thickness has been reported in this paper. It was observed that the aluminium based MCPCBs performed better heat dissipation compared to the copper based MCPCBs. In addition, when two different thicknesses of the MCPCB substrates were compared, it was observed that the thicker substrate performed a lower thermal resistance compared to the thinner substrate MCPCB. The junction to board thermal resistance was determined using the standard transient dual interface method.