(Invited) How to Achieve Low Thermal Resistance and High Electrothermal Ruggedness in Ga2O3 Devices?

Abstract

Ultra-wide-bandgap semiconductor gallium oxide (Ga2O3) has been promoted for years as a promising candidate for power electronics and RF applications, due to its high critical electrical field, controllable n-type doping, and the availability of large-diameter wafers by the melt growth. However, a fundamental limitation of Ga2O3 is its low thermal conductivity (k T = 0.1-0.3 Wcm-1K-1), which is about 1/6 of the k T of Si, 1/10 of GaN, and 1/20 of SiC. The resulting high thermal resistance of Ga2O3 chip has brought serious concerns regarding the current and power scalability of Ga2O3 devices and their electrothermal ruggedness. As a result, questions have persisted on the true viability of Ga2O3 devices in industrial power and RF applications.Despite some simulation and modeling works on the Ga2O3 thermal management, there has been no experimental report on the packaging and thermal management of large-area Ga2O3 devices. The lack of these data makes it difficult to compare Ga2O3 with commercial device technologies (e.g., Si, SiC, GaN) and evaluate the application space of Ga2O3 devices. Some recent works characterized the channel (or junction) temperatures in Ga2O3 devices, but all of these devices have small areas with a current much lower than 1 Amp, and none of these devices are packaged.This work presents the first experimental demonstration of large-area Ga2O3 devices and their thermal management through device-package co-optimization. Vertical Ga2O3 Schottky barrier diodes (SBDs) with a 3×3 mm2 Schottky contact area were fabricated with an on/off ratio over 1010, a forward current over 20 A, and a reverse breakdown voltage over 600 V. These large-area Ga2O3 SBDs were packaged in the bottom-side-cooling and double-side-cooling configurations using the nanosilver sintering as the die attach and the silver plate as the thermal pad.Surge current ruggedness is an essential ruggedness metric listed in any power diode’s datasheet and the most important indicator of a device’s transient electrothermal ruggedness. It measures the device’s capability of temporarily sustaining a current much higher than the rated current. To evaluate the surge current ruggedness of packaged Ga2O3 devices, a surge-current test circuit was prototyped to produce a 10-ms-wide half-sinusoidal current waveform based on the JEDEC standard. The surge-current tests revealed a critical surge current of 37.5 A for the single-side-packaged Ga2O3 SBD and 68 A for the double-side-packaged Ga2O3 SBD. The ratio between the peak surge current and the rated current of the double-side-packaged Ga2O3 SBD was found to be superior to that of similarly-rated commercial SBDs.The key enabling mechanisms for this superior-to-SiC surge current capability are two-fold: first, the fabricated Ga2O3 SBD shows a smaller temperature dependence of on-resistance as compared to the SiC SBDs, which strongly reduces the thermal runaway; second, the double-side-packaging allows the heat to be extracted directly from the Schottky junction without the need for going through the low-k T bulk Ga2O3 chip.To further evaluate the steady-state thermal performance of these Ga2O3 SBDs, the junction-to-case thermal resistance (R θJC) of a double-side-packaged Ga2O3 SBD was measured in the bottom-side- and junction-side-cooling configurations. The R θJC characterization is based on the transient dual interface method, i.e., JEDEC 51-14 standard. The R θJC of the junction- and bottom-cooled Ga2O3 SBD was measured to be 0.5 K/W and 1.43 K/W, respectively, with the former R θJC lower than that of similarly-rated commercial SiC SBDs. This low R θJC is attributable to the heat extraction directly from the Schottky junction instead of through the Ga2O3 chip.The higher surge current ruggedness and lower thermal resistance demonstrated in a large-area, packaged Ga2O3 SBD as compared to the similarly-rated SiC devices proves the viability of Ga2O3 devices for high-power applications. Note that no complex or costly process, such as substrate thinning and layer transfer, has been applied to our Ga2O3 chip. These results manifest that device-packaging co-optimization is an effective and low-cost approach for the thermal management of Ga2O3 devices.