Transfer Torque Magnetoresistive Random Access Research Articles

FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement

Spin transfer torque (STT) magneto-resistive random access memory (MRAM)-based non-volatile logic circuits require asymmetric write current to enable high efficiency. This requires methods at the device or circuit level to meet the asymmetric current requirement of STT MRAM-based circuits. In this work, we propose a novel asymmetric fin field-effect transistor (FinFET)-based access device, along with a process flow, at a 3-nm node. The proposed device uses selective fin-trimming during the replacement metal gate (RMG) process, along with a dielectric deposition in the trimmed fin regions. This process does not require a new mask design and can be easily integrated into standard CMOS technology, and thus is very attractive with respect to previously proposed devices. With 3-D TCAD modeling, we show that up to 26% asymmetricity can be achieved with this device architecture, which meets the requirement of STT MRAM-based circuits. The proposed device offers 30% lower gate capacitance with respect to previously proposed devices.

Spin Transfer Torque Evaluation Based on Coupled Spin and Charge Transport: A Finite Element Method Approach

Emerging spin transfer torque magnetoresistive random access memories (STT MRAM) are nonvolatile and offer high speed and endurance. MRAM cells include a fixed reference magnetic layer and a free-to-switch ferromagnetic layer (FL), separated by a tunnel barrier. The FL usually consists of several sub-layers separated by nonmagnetic buffer layers. The magnetization dynamics is governed by the Landau-Lifshitz-Gilbert (LLG) equation supplemented with the corresponding torques. To accurately design MRAM cells it is necessary to evaluate the torques in composite magnetic layers, which depend on nonequilibrium spin accumulation generated by an electric current. Spin accumulation and current also depend on the magnetization. Therefore, the LLG and the spin-charge transport equations must be solved simultaneously. We apply the finite element method (FEM) to numerically solve this coupled system of partial differential equations. We follow a modular approach and use well-developed C++ FEM libraries. For the computation of the torques acting in a magnetic tunnel junction (MTJ), a magnetization-dependent resistivity of the tunnel barrier is introduced. A fully three-dimensional solution of the equations is performed to accurately model the torques acting on the magnetization. The use of a unique set of equations for the whole memory cell is an ultimate advantage of our approach.

Temperature increase in STT-MRAM at writing: A fully three-dimensional finite element approach

The writing process in spin transfer torque magnetoresistive random access memories (STT-MRAM) is facilitated by elevated temperatures. In this work we investigate the temperature distribution and development in the free layer (FL) of an STT-MRAM during switching. With our fully three-dimensional (3D) finite element method simulation approach, we numerically solve the heat transport equation coupled to the electron, spin, and magnetization dynamics and demonstrate that the FL temperature is highly inhomogeneous due to the non-uniform magnetization of the FL during switching for an STT-MRAM with large magnetic tunnel junction (MTJ) diameter. While the average temperature in the FL can be obtained based on an average current density and an averaged potential drop across the tunnel barrier, a fully 3D model is required to evaluate the large local temperature variations. The temperature variations in the FL further increase, when realistic device structures with an MTJ coated by a passivation layer and contacted to broad electrodes are considered. Lowering the FL thermal conductivity increases the temperature variations even further. However, the variations are strongly reduced with the decrease of the MTJ diameter.

Interface imperfection effects on spin transfer torque switching: an atomistic approach

The further commercialization of spintronic memory devices depends on the development of methods by which to assess performance. This paper presents an approach to the atomistic investigation of switching performance in spin transfer torque magneto-resistive random access memory (MRAM) devices with the use of interface imperfection model. Switching simulation in the nanosecond regime was made possible under this model, and we first time demonstrate that switching time is inversely proportional to interface imperfection (i.e. roughness). In investigating the damping of CoFeB/MgO films, we analyzed the effective damping constant α eff, which cannot be accurately predicted for ferromagnetic layers of less than 2 nm using existing micromagnetic models. The proposed model includes a roughness parameter, which has nearly no effect on the effective damping constant in films of >2 nm, but a profound effect in films of <2 nm, reaching a 27% decrease in a 1.0 nm CoFeB film. Our finding is supported by the experimental data of classic references. We expect that these results will prove valuable in magnetic simulation and research on MRAM with ultrathin films.

Hybrid buffers based coarse-grained power gated network on chip router microarchitecture

ABSTRACTWith the failure of Dennard’s Scaling, we cannot power on all the transistors of an circuit simultaneously for a given thermal design power. In this paper, we propose coarse-grained power gated hybrid buffer based Network on Chip router microarchitecture which a large amount of Network on Chip router power and area is consumed by the FIFO buffers. State of the art NoC router buffers is composed of SRAM, which is neither power efficient nor area efficient. We have proposed hybrid buffers based coarse-grained power gated Network on Chip router microarchitecture. As STT-MRAM (Spin Transfer Torque Magneto-resistive Random Access Memory) provides an improved solution having near zero leakage power and higher package density. Our proposed router microarchitecture improves 12.3% average packet latency as compared to state of the art power gated SRAM based router and 4.90% as compared to the fine-grained power gated hybrid buffer based router respectively for PARSEC benchmarks. We have achieved 65% and 21.34% total network energy saving for PARSEC benchmarks as compared with one without power gating and state of the art power gated SRAM based router respectively. Our hybrid router is 35.10% area efficient as compare to pure SRAM based power gated router at 32nm technology node.

Resonant Spin-Transfer Torque Magnetoresistive Memory

Spin transfer torque magnetoresistive random access memory (STT-MRAM) has shown a great promise to be a main stream novel nonvolatile memory technology. Reduction of state switching current still remains to be a continued research focus for scaling down the size of the addressing transistors. One of the switching characteristics attributing to the relatively high power consumption is the asymmetry of switching current threshold: switching from parallel (P) to antiparallel (AP) state requires more than twice as much current as switching from antiparallel to parallel state. In this paper, we present a design that can significant reduce the switching current threshold for switching from P to AP state to substantially reduce or eliminate the switching asymmetry. By incorporating an antiferromagnetic/ferromagnetic stack to provide a rotating spin transfer torque that matches with the ferromagnetic resonance frequency of the free layer, switching threshold can be significantly reduced.

Write energy reduction of STT-MRAM based multi-core cache hierarchies

ABSTRACTSpin transfer torque magnetoresistive random access memory (STT-MRAM) is a favourable memory technology for on-chip cache hierarchies in multi-core processors. STT-MRAM offers scalability, near zero leakage power, non-volatility, high density, etc., which makes it a good candidate for on-chip cache memory. However, write access latency and write energy consumption in STT-MRAM is relatively high as compared to traditional SRAM which results in high dynamic power consumption as well as performance degradation. In this paper, we have analysed the impact of write buffers on the STT-MRAM-based cache hierarchy. We have tried to optimise the write operations in L1 and L2 cache by exploiting the small static random access memory-based write buffers. The write operations are redirected to the write buffer and not to the L1 cache which mitigates the energy and performance overhead induced by STT-MRAM write operations. Experiment results on PARSEC benchmark show that STT-MRAM-based cache hierarchy improves 90% static energy. But due to large write energy and latency, the dynamic energy of STT-MRAM-based cache is 12.53% higher than the SRAM-based cache hierarchy. The normalised execution time is improved by 19.33% as compared to SRAM-based cache hierarchy.

High performance perpendicular magnetic tunnel junction with Co/Ir interfacial anisotropy for embedded and standalone STT-MRAM applications

High volume spin transfer torque magnetoresistance random access memory (STT-MRAM) for standalone and embedded applications requires a thin perpendicular magnetic tunnel junction (pMTJ) stack (∼10 nm) with a tunnel magnetoresistance (TMR) ratio over 200% after high temperature back-end-of-line (BEOL) processing up to 400 °C. A thin reference layer with low magnetic moment and strong perpendicular magnetic anisotropy (PMA) is key to reduce the total thickness of the full pMTJ stack. We demonstrated strong interfacial PMA and a perpendicular Ruderman-Kittel-Kasuya-Yosida exchange interaction in the Co/Ir system. Owing to the additional high PMA at the Ir/Co interface in combination with a conventional CoFeB/MgO interface in the Ir/Co/Mo/CoFeB/MgO reference layer, the full film pMTJ showed a TMR ratio over 210% after annealing at 400 °C for 150 min. The high TMR ratio can be attributed to the thin stack design by combining a thin reference layer with the efficient compensation by a thin pinned layer. The annealing stability may be explained by the absence of solid solution in the Co-Ir system and the low oxygen affinity of Mo in the reference layer and the free layer. High device performance with a TMR ratio over 210% was also confirmed after subjecting the patterned devices to BEOL processing temperatures of up to 400 °C. This proposed pMTJ design is suitable for both standalone and embedded STT-MRAM applications.

A Comparative Study Between Spin-Transfer-Torque and Spin-Hall-Effect Switching Mechanisms in PMTJ Using SPICE

The spin transfer torque magnetoresistive random access memory (STT-MRAM) is the leading candidate for spin-based memories. Nevertheless, the high write energy and read disturbance of the STT-MRAM motivated researchers to find other solutions. The spin Hall effect (SHE)-based MRAM is an alternative for the STT-MRAM, which also provides nonvolatility, zero leakage, and competitive area per bit, but with a lower write current. This paper focuses on a systematic performance analysis of these two proposed memory solutions. The SHE requires an external field to deterministically switch perpendicular magnetic anisotropy magnetic tunnel junction (MTJ). A previous experiment showed that the SHE can switch composite MTJ containing an in-plane layer without any field. In this paper, both traditional and composite MTJ structures are modeled in SPICE, which can reproduce realistic MTJ characteristics with user-defined input parameters. This self-contained model is used to compare the write energy and delay of the STT-MRAM and the SHE magnetoresistive random access memory (SHE-MRAM) for various write schemes including thermal fluctuation. Our simulations show, compared with the STT-MRAM, that the SHE-MRAM improves the write delay and the energy by eight times and seven times, respectively. Based on our extensive analysis incorporating the latest advances in magnetic materials and device technology, we predict that the SHE-MRAM is a feasible low-energy memory solution for future computing systems.

Long-term reliable physically unclonable function based on oxide tunnel barrier breakdown on two-transistors two-magnetic-tunnel-junctions cell-based embedded spin transfer torque magnetoresistive random access memory

Among the diverse applications of spintronics, security for internet-of-things (IoT) devices is one of the most important. A physically unclonable function (PUF) with a spin device (spin transfer torque magnetoresistive random access memory, STT-MRAM) is presented. Oxide tunnel barrier breakdown is used to realize long-term stability for PUFs. A secure PUF has been confirmed by evaluating the Hamming distance of a 32-bit STT-MRAM-PUF fabricated using 65 nm CMOS technology.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Stochastic macromodel of magnetic tunnel junction resistance variation and critical current dependence on resistance variation for SPICE simulation

The resistance distribution of a magnetic tunnel junction (MTJ) shows nonuniformity according to various MTJ parameters. Moreover, this resistance variation leads to write-current density variation, which can cause serious problems when designing peripheral circuits for spin transfer torque magnetoresistance random access memory (STT-MRAM) and commercializing gigabit STT-MRAM. Therefore, a macromodel of MTJ including resistance, tunneling magnetoresistance ratio (TMR), and critical current variations is required for circuit designers to design MRAM peripheral circuits, that can overcome the various effects of the variations, such as write failure and read failure, and realize STT-MRAM. In this study, we investigated a stochastic behavior macromodel of the write current dependence on the MTJ resistance variation. The proposed model can possibly be used to analyze the write current density in relation to the resistance and TMR variations of MTJ with various parameter variations. It can be very helpful for designing STT-MRAM circuits and simulating the operation of STT-MRAM devices considering MTJ variations.

Switching Time and Stability Evaluation for Writing Operation of STT-MRAM Crossbar Array

The dynamic characteristics of a spin transfer torque magnetoresistive random access memory crossbar array during write operations were investigated. A spin transfer torque magnetic tunnel junction was combined with a two-terminal selector device instead of a three-terminal CMOS transistor in the crossbar array architecture. The characteristics of the crossbar array architecture were investigated under different bias schemes and transient simulations of write operations were performed under various operating conditions. The variance of the switching time and problematic behaviors was investigated. The floating bias scheme was compared with the 1/2 bias scheme, and simulation results revealed that write errors may be induced in the floating bias scheme by abnormal glitches occurring when the parasitic capacitance becomes large.

Performance Enhancement of STT MRAM Using Asymmetric- Sidewall-Spacer NMOS

Conventional spin transfer torque (STT) magneto-resistive random access memory (MRAM) generally includes a bulk n-channel MOS (NMOS) transistor as an access device that provides equal drive current in standalone conditions in both the directions. However, the switching current requirement of magnetic tunnel junctions (MTJs) in STT MRAM is highly asymmetric (2 to 3:1). With conventional access devices, the excess write current in one direction maps to unnecessarily higher power dissipation. Hence, in this paper, a novel STT MRAM cell with an asymmetric-dielectric (asymmetric- $k$ ) sidewall-spacer NMOS (ASNMOS) is presented. ASNMOS has different- $k$ sidewall spacers, i.e., one side high- $k$ and other side low- $k$ spacer. As desired, this novel ASNMOS provides asymmetric drive current and reduces the overall power dissipation. The proposed STT MRAM cell is analyzed with HSPICE simulations using calibrated Verilog-A models for access device and perpendicular magnetic anisotropy MTJ. The STT MRAM cell with the proposed ASNMOS exhibits up to 25% reduction in the dynamic power dissipation over the STT MRAM cell with the conventional symmetric NMOS as an access device. Moreover, ASNMOS-based cells shows higher reliability wherein the worst case current density through MTJ is reduced by 25%.

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM

The capacity of embedded memory on LSIs has kept increasing. It is important to reduce the leakage power of embedded memory for low-power LSIs. In fact, the ITRS predicts that the leakage power in embedded memory will account for 40% of all power consumption by 2024 [1]. A spin transfer torque magneto-resistance random access memory (STT-MRAM) is promising for use as non-volatile memory to reduce the leakage power. It is useful because it can function at low voltages and has a lifetime of over 1016 write cycles [2]. In addition, the STT-MRAM technology has a smaller bit cell than an SRAM. Making the STT-MRAM is suitable for use in high-density products [3–7]. The STT-MRAM uses magnetic tunnel junction (MTJ). The MTJ has two states: a parallel state and an anti-parallel state. These states mean that the magnetization direction of the MTJ’s layers are the same or different. The directions pair determines the MTJ’s magneto- resistance value. The states of MTJ can be changed by the current flowing. The MTJ resistance becomes low in the parallel state and high in the anti-parallel state. The MTJ potentially operates at less than 0.4 V [8]. In other hands, it is difficult to design peripheral circuitry for an STT-MRAM array at such a low voltage. In this paper, we propose a counter-based read circuit that functions at 0.4 V, which is tolerant of process variation and temperature fluctuation.

(Invited) Low Power Stt-Mram and Its Application to Normally-Off Processor

Reduction of the power consumption of mobile electronic devices is one of the principal issues in current and future electronics technology. In particular, reducing the power consumption of the processor is critical because it increases as the processor’s performance improves. Normally-off computing is one of the solutions. Standby power of a cache memory while the device power is on but the memory is idle accounts for a large proportion of the processor’s power consumption, which can be eliminated by shutting down the cache memory during the idle time and turning it on instantly when the memory becomes active. The key technology for the normally-off processor to reduce power effectively is a fast, low-power, non-volatile memory for the cache memory to replace the current SRAM cache memory. Among the various non-volatile memories, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is the most promising candidate for the cache memory of the normally-off processor because of its potential performance in terms of fast switching and scalability. A magnetic tunnel junction (MTJ) storage element having perpendicular magnetization (p-MTJ) reduces the writing current of the STT-MRAM, which enables scaling of the STT-MRAM. However, for power saving of the normally-off processor, small write current and short write pulse duration time must be achieved simultaneously. In other words, write charge, which is write current multiplied by write pulse width, is a key parameter for power saving. Toshiba demonstrated STT switching of the p-MTJ with write charge of 90 fC whose write pulse width was 1 ns and write current was 90 uA. Simulation of the processor’s power consumption with this STT MRAM showed good power saving. Landau–Lifshitz–Gilbert (LLG) micromagnetic simulation of spin-transfer torque shows that a coherent precession of the spin plays an important role for fast switching of the p-MTJ. Initially, when the write current is applied to the p-MTJ, each spin precesses independently and the spin stays in the initial direction. It corresponds to incubation delay time. Immediately after the precession of each spin is synchronized and rotates coherently, switching of the spin begins. Therefore, the coherency of the spin precession needs to be controlled for further improvement of the fast switching of the p-MTJ. A part of this work was supported by NEDO.

Perpendicular magnetic tunnel junction with thin CoFeB/Ta/Co/Pd/Co reference layer

Integration of high density spin transfer torque magnetoresistance random access memory requires a thin stack (less than 15 nm) of perpendicular magnetic tunnel junction (p-MTJ). We propose an innovative approach to solve this challenging problem by reducing the thickness and/or moment of the reference layer. A thin reference layer structure of CoFeB/Ta/Co/Pd/Co has 60% magnetic moment of the conventional thick structure including [Co/Pd] multilayers. We demonstrate that the perpendicular magnetization of the CoFeB/Ta/Co/Pd/Co structure can be realized by anti-ferromagnetically coupling to a pinned layer with strong perpendicular anisotropy via Ruderman-Kittel-Kasuya-Yosida exchange interaction. The pMTJ with thin CoFeB/Ta/Co/Pd/Co reference layer has a comparable TMR ratio (near 80%) as that with thick reference layer after annealing at 280 °C. The pMTJ with thin reference layer has a total thickness less than 15 nm, thereby significantly increasing the etching margin required for integration of high density pMTJ array on wafers with form factor of 300 mm and beyond.

In situ X-ray photoelectron spectroscopy study of gas cluster ion beam etching of FeCo film

FeCo films of the type used in spin transfer torque magnetoresistive random access memory were etched by gas cluster ion beam (GCIB) irradiation with acetic acid vapor and characterized by in situ X-ray photoelectron spectroscopy. After 20 keV O2-GCIB irradiation with acetic acid vapor, etching depth enhancement (10.7×) was observed compared with the results without acetic acid vapor. The etching model of FeCo can be described as follows: (1) FeCo oxide formation with O2-GCIB irradiation, (2) acetic acid adsorption on FeCo oxide, (3) reactions between FeCo oxide and acetic acid, and (4) the desorption of volatile compounds by local and transient heating owing to O2-GCIB bombardment. Cross-sectional transmission electron microscopy, transmission electron diffraction analysis, and electron energy loss spectroscopy results showed no significant etching damage or oxidation of FeCo films after etching by O2-GCIB irradiation with acetic acid vapor. Therefore, the low-damage etching of FeCo can be performed by O2-GCIB irradiation with acetic acid vapor.

Physics-Based SPICE-Compatible Compact Model for Simulating Hybrid MTJ/CMOS Circuits

A simulation framework that can comprehend the impact of material changes from the device level to the system level design can be of great value, especially to evaluate the impact of emerging devices on various applications. To that effect, we developed a SPICE-based hybrid magnetic tunnel junction (MTJ)/CMOS simulator, which can be used to explore new opportunities in large scale system design. In the proposed simulation framework, MTJ modeling is based on Landau-Lifshitz-Gilbert (LLG) equation incorporating both spin-torque and external magnetic field(s). LLG, along with heat diffusion equation, thermal variations, and electron transport, is implemented using SPICE-in-built voltage-dependent current sources and capacitors. The proposed simulation framework is flexible because the physical device parameters such as MgO thickness, ferromagnet material anisotropy (Ku), and device dimensions are user-defined parameters. Furthermore, we benchmarked this model with experiments in terms of switching current density (JC), switching time (TSWITCH), and tunneling magnetoresistance. Finally, we used the simulation framework to study different MTJ structures, such as in-plane magnet anisotropy and perpendicular magnet anisotropy, the impact of parametric process variations and temperature on the yield of spin transfer torque magnetoresistive random access memories, magnetic flip-flops, and spin-torque oscillators.