Transfer Gate Research Articles

Computer model and charge transport studies in short gate charge-coupled devices

A computer model has been developed that simulates charge transport of carriers in a surface channel charge-coupled device. This model is based on the charge continuity and current transport equations with a time dependent surface field. The device structure of the model includes a source diffusion an input gate and transfer gate. The present model is the first real simulation of the input scheme of the surface-channel CCDs. The scooping and spilling techniques associated with the charge injection process are simulated by the input diffusion which is included in the model. As an application to a CCD practical problem the present model has been used to study the linearity of the electrical charge injection into surface channel charge-coupled devices. The generated harmonic components of a sinusoidal input are calculated using the transfer characteristics of the input stage obtained from the computer simulation. Using this model the spatial variations of the self-induced fringing field and total currents under the storage and transfer gates were computed. The charge transfer mechanisms for short-gate ( L ≤ 8 μm) CCDs was investigated. It was found that for short gates the charge transfer efficiency is governed mainly by the fringing field and self-induced current mechanisms. The results of this study help to clarify the mechanism by which the signal-charge level and gate length affect the charge transfer efficiency.

68 kbit capacity 16 µm-period magnetic bubble memory chip design with 2 µm minimum features

A bubble propagating structure that operates well on a 14 μm to 18 μm propagate period with a nominal 2 μm minimum feature size has been designed. The structure consists of only 1 discrete permalloy feature per circuit period. Sixty-eight kbit-capacity memory chips based on such structures have been designed, built, characterized, packaged and the packages have been characterized. The chip is organized as a set of minor (storage) loops with separate write and read major lines. The bubble manipulating functions, of which the replicate and transfer gates are the most critical, have also been designed with 2 μm minimum features. The design is adequate to provide a 14 Oe bias field margin range with drive fields of about 35 Oe, using a bubble garnet material with approximately 170 Oe free bubble collapse field. Sixty-eight kbit single loop shift register type chips designed using similar propagating structures, however, provide over 20 Oe bias field margin ranges with drive fields of about 35 Oe.

The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.

The charge-coupled RAM cell concept

A new concept in MOS dynamic RAM cells is described and demonstrated. The charge-coupled RAM (CC RAM) cell combines the storage capacity and transfer gate of the one-transistor cell into a single gate. The resulting cell is simpler than the conventional one-transistor cell and possesses significant advantages in packing density and potentially higher yield. One of the variations of the CC RAM cell concept results in a cell whose operation is identical (voltage and timing) to that of the present one-transistor cell. In addition, the CC RAM cell fabrication is essentially the same as the present one-transistor cell process. The CC RAM is an attractive candidate for the next generation RAM's.

A 4Kbit bubble memory chip using X-bar propagation patterns

The design and operation margins of a bubble memory chip 2,8 mm × 2,1 mm with 32 minor loops of 128 bits of storage capacity each are described. In a special package, designed for test purposes and containing the drive field coils and a variable bias magnet system, signals up to 10 mV are generated by bubbles of 6 μm diameter in a thin film detector. The X-bar propagation works well up to 500 kHz using garnets having the composition Y 1,6 Sm 0,4 Ca 1 Fe 3,9 Ge 1 Si 0,1 O 12 . Also the transfer is performed by special X-bar transfer gates.

Radiation Effects in Charge Coupled Devices

Charge coupled devices (CCD s) exhibit a number of advantages (low cost, low power, high bit density) in their several applications (serial memories, imagers, digital filters); however, fairly elementary theoretical considerations indicate that they will be very vulnerable to permanent radiation damage, by both neutrons and ionizing radiation, and to transient upset by pulsed ionizing radiation. Although studies of permanent ionizing-radiation damage in CCD's have been reported, little information has been published concerning their overall nuclear radiation vulnerability. This paper presents a fairly comprehensive experimental study of radiation effects in a 256-cell surface-channel, CCD shift- register. A limited amount of similar work is also presented for a 128-cell surface-channel device and a 130 cell peristaltic CCD shift register. The radiation effects phenomena discussed herein, include transient-ionizing- radiation responses, permanent ionizing- radiation damage to transfer efficiency, charge-carrying capacity and input transfer gate bias, and neutron damage to storage time--determined from dark current and charge-up time measurements. (auth)

An all-permalloy bubble memory with control functions based on drive-field operation

A small experimental bubble memory chip with the major-minor loop organization has been designed and tested under laboratory conditions. As distinct from the conventional current-controlled memories, the necessary functions are operated by a temporary change of rotation of the drive field. Using this method a design is possible for which in practice only one mask is needed. The transfer gates, used in the control elements, are discussed extensively as also are the generator- and annihilator-locks, which are necessary for chip selection. The specific properties of this memory are compared with those of a current-controlled memory.

The "Single-conductor and ratch" bubble propagating circuit

A single-phase vertical-field bubble propagating circuit is described. High-speed bubble propagation along a single-conductor line is realized to give an oscillating bias field driven by a monopolar current pulse in the conductor to the magnetostatically trapped bubbles in ratch patterns. The relation between the pulse amplitude and the propagation distance of the bubble is analyzed. A two-way propagating circuit useful for the transfer gate is realized, based on the transverse motion of bubbles. Loop circuits, transfer gates, and a generator circuit as well as various shift registers have been designed and tested. The propagation speed of 1 MHz could be obtained under the applied current of 800 mA, using YFeO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> crystal platelet of thickness 80μm, the conductor of width 30μm, and the ratch patterns of period 110μm. A structure of a major/minor loop organized memory circuit with a function of dynamic reallocation of data is proposed.

Magnetic bubble memory chip design

The choice and organization of bubble-circuit functions in the design of a magnetic bubble mass memory chip are discussed with emphasis on factors such as circuit function compatibility and performance, circuit density, and processing simplicity. A specific major-minor organized chip design is described which uses rotating field driven propagation, $-sign transfer gates, all T-bar minor loops, a nucleate generator with chevron merging port, a chevron based replicator/ annihilator and a chevron guard rail expander detector. The overall operating characteristics of chips having 20 510 bits of storage capacity have been measured and a bias field margin of 12 Oe is typically obtained with a 25 Oe, 100 kHz rotating field.

A gated ion source for time-of-flight spectroscopy

A gated ion source using tetrode geometry and having 100% gating efficiency for all ion species is described. Static transfer characteristics and gating characteristics are presented, and the effect of other charge states on the space charge limited current of a given ion species is discussed.

D2 Channel Bank: Multiplexing and Coding

Analog multiplexing and coding in the D2 Channel Bank is discussed in this article. Multiplexing of the message signals is accomplished in two stages. In the first stage, groups of 12 channels are multiplexed together using resonant transfer gates. The resulting eight buses,' each carrying pulse-amplitude-modulated signals of 12 channels, are then multiplexed in the second stage. The samples of all 96 channels are presented to a single coder. The demultiplexing plan follows the inverse of the multiplexing plan. The output of the decoder is first divided into eight buses, and the final demultiplexing is accomplished in groups of 12 channels. Because the decoding is accomplished by an asynchronous time-shared decoder, storing and stretching of the analog samples is necessary to permit removal of the time jitter due to the queuing process. The coder used in D2 is a nonlinear coder using a compression characteristic called the 15-segment approximation to the µ = 255 law. To ensure the success of the coder development, a stage-by-stage binary coding plan was chosen. The first stage determines the polarity of the signal, and the succeeding binary stages determine the amplitude of the compressed signal one digit at a time. To achieve accuracy in the coder with available devices, automatic zero-setting circuits are used in a feedback loop to control offset deviations. This is in addition to the use of precision resistors and precision power supplies for the remaining critical parts of the coder. In order to achieve comparable accuracy in the decoder, the same stage-by-stage arrangement is also used. Again, automatic zero-set feedback loops are used to control drifts. The performance of the coder/ decoder combination has met the objectives.