Gate Voltage Transfer Research Articles

Analytical Modeling of Potential Barrier for Charge Transfer in Pinned Photodiode CMOS Image Sensors

A potential barrier is one of the most common lag sources for charge transfer in pinned photodiode (PPD) CMOS image sensors (CISs). In this article, an analytical model of the potential barrier is proposed for the PPD combined with the transfer gate (TG). Through detailed electrostatic analysis of the PPD and TG, the potential barrier is analytically expressed as a function of the doping concentrations, TG voltage, spatial dimensions, and other physical parameters. The proposed model is validated by technology computer-aided design (TCAD) simulations, and the results show that the model data are in good agreement with the TCAD simulations in terms of the magnitude and location of the potential barrier. The model can be used for the design, simulation, and optimization of PPD-based pixels in CISs to improve the charge transfer efficiency (CTE) and reduce the image lag noise.

Hydrogen incorporation into amorphous indium gallium zinc oxide thin-film transistors

An experimental study is conducted in which the subgap trap density of states (DoS) is measured by ultrabroadband photoconduction (UBPC) to examine hydrogen incorporation into the channel layer of top-gate amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs). UBPC reveals that hydrogen incorporation leads to the creation of a spectrally broad (∼0.3 eV FWHM) distribution of electronic states in the bandgap centered at 0.4 eV above the valence band mobility edge and to an increase in valence band tail state density. Concomitantly, drain current–gate voltage transfer curves demonstrate that hydrogen incorporation results in a negative shift in the turn-on voltage. Quantitatively, electronic state densities estimated by UBPC and the turn-on voltage shift are identical. These experimental findings imply that hydrogen acts as a donor in a-IGZO, but that its donor ionization energy is extraordinarily large, i.e., ∼2.8 eV, inconsistent with that of a normal donor. It is proposed that this anomalous donor behavior is a consequence of the negative-U property of hydrogen in a-IGZO in which hydrogen ionization precedes its incorporation into the lattice network.

Nanoscale Mapping of the Conductivity and Interfacial Capacitance of an Electrolyte‐Gated Organic Field‐Effect Transistor under Operation

AbstractProbing nanoscale electrical properties of organic semiconducting materials at the interface with an electrolyte solution under externally applied voltages is key in the field of organic bioelectronics. It is demonstrated that the conductivity and interfacial capacitance of the active channel of an electrolyte‐gated organic field‐effect transistor (EGOFET) under operation can be probed at the nanoscale using scanning dielectric microscopy in force detection mode in liquid environment. Local electrostatic force versus gate voltage transfer characteristics are obtained on the device and correlated with the global current–voltage transfer characteristics of the EGOFET. Nanoscale maps of the conductivity of the semiconducting channel show the dependence of the channel conductivity on the gate voltage and its variation along the channel due to the space charge limited conduction. The maps reveal very small electrical heterogeneities, which correspond to local interfacial capacitance variations due to an ultrathin non‐uniform insulating layer resulting from a phase separation in the organic semiconducting blend. Present results offer insights into the transduction mechanism at the organic semiconductor/electrolyte interfaces at scales down to ≈100 nm, which can bring substantial optimization of organic electronic devices for bioelectronic applications such as electrical recording on excitable cells or label‐free biosensing.

Comparative study of aluminum and nickel contact electrodes for indium–tin–zinc oxide thin film transistors using oxygen vacancy diffusion model

We fabricate amorphous indium–tin–zinc oxide (ITZO) thin film transistors (TFTs), in which the source/drain (S/D) electrodes are composed of metallic Al and nickel Ni. We experimentally investigate the contact characteristics of Al and Ni S/D electrodes using the transmission line method. The ITZO with Al exhibits low field-effect mobility (≤4.8 cm2/Vs) and behaves like a conductor at short channel lengths. Even with a short channel length, the ITZO with Ni exhibits typical field-effect TFT behavior and high field-effect mobility (≥8.1 cm2/Vs), required for a high-resolution display. We present a mechanism to dope oxygen vacancies in the S/D regions to account for the differences in the properties of the ITZO TFTs with Al and Ni electrodes. Using a technology computer-aided design (TCAD) simulation, we show that the oxygen vacancies (VO+) could diffuse from the Al and Ni S/D electrodes at a substrate temperature of 350 °C in 30 min, and find that their diffusion coefficient and activation energy are 2.8 × 10−8 cm2/s and 0.45 eV, respectively. Further, the S/D doping concentrations of VO+ are 3.47 × 1019 and 1.55 × 1017/cm3 at the Al and Ni interfaces, respectively. The lateral diffusion profiles of VO+ are different for the Al and Ni electrodes, which caused a difference in the drain current to gate voltage transfer characteristics of each electrode.

The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

Recent Enhancements to Interline and Electron Multiplying CCD Image Sensors.

This paper describes recent process modifications made to enhance the performance of interline and electron-multiplying charge-coupled-device (EMCCD) image sensors. By use of MeV ion implantation, quantum efficiency in the NIR region of the spectrum was increased by 2×, and image smear was reduced by 6 dB. By reducing the depth of the shallow photodiode (PD) implants, the photodiode-to-vertical-charge-coupled-device (VCCD) transfer gate voltage required for no-lag operation was reduced by 3 V, and the electronic shutter voltage was reduced by 9 V. The thinner, surface pinning layer also resulted in a reduction of smear by 4 dB in the blue portion of the visible spectrum. For EMCCDs, gain aging was eliminated by providing an oxide-only dielectric under its multiplication phase, while retaining the oxide-nitride-oxide (ONO) gate dielectrics elsewhere in the device.

A Dynamic Range Extension Technique for CMOS Image Sensors With In-Pixel Dual Exposure Synthesis

This paper presents an in-pixel dual exposure synthesis technique to extend dynamic range of CMOS image sensors (CISs). The transfer transistor of the 4-T pixel acts as an overflow transistor in this proposed method. The full well capacity of photodiode (PD) can be very well controlled by biasing the transfer gate at different states. The long and short time exposed signals can be both stored in PD by adjusting the transfer gate voltage, and such the wide dynamic range signal can be obtained without extra readout operation. A proto chip with $64 \times 48$ pixel array is fabricated in 0.18- $\mu $ m CIS process. The sensor structure is based on a typical 4-T pixel image sensor with modified transfer gate driver and timing. This structure not only maintains the good features of 4-T pixels, such as good fill factor and low noise, but also achieves a wide dynamic range. The dynamic range of the proto chip is extended from 51.59 to 90.53 dB.

A Wide Dynamic Range CMOS Image Sensor Based on a Pseudo 3-Transistor Active Pixel Sensor Using Feedback Structure

A dynamic range extension technique is proposed based on a 3-transistor active pixel sensor (APS) with gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector using a feedback structure. The new APS consists of a pseudo 3-transistor APS and an additional gate/body-tied PMOSFET-type photodetector, and to extend the dynamic range, an NMOSFET switch is proposed. An additional detector and an NMOSFET switch are integrated into the APS to provide negative feedback. The proposed APS and pseudo 3-transistor APS were designed and fabricated using a 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) process. Afterwards, their optical responses were measured and characterized. Although the proposed pixel size increased in comparison with the pseudo 3-transistor APS, the proposed pixel had a significantly extended dynamic range of 98 dB compared to a pseudo 3-transistor APS, which had a dynamic range of 28 dB. We present a proposed pixel that can be switched between two operating modes depending on the transfer gate voltage. The proposed pixel can be switched between two operating modes depending on the transfer gate voltage: normal mode and WDR mode. We also present an imaging system using the proposed APS.

Revisiting MOSFET threshold voltage extraction methods

This article presents an up-to-date review of the several extraction methods commonly used to determine the value of the threshold voltage of MOSFETs. It includes the different methods that extract this quantity from the drain current versus gate voltage transfer characteristics measured under linear operation conditions for crystalline and non-crystalline MOSFETs. The various methods presented for the linear region are adapted to the saturation region and tested as a function of drain voltage whenever possible. The implementation of the extraction methods is discussed and tested by applying them to real state-of-the-art devices in order to compare their performance. The validity of the different methods with respect to the presence of parasitic series resistance is also evaluated using 2-D simulations.

Amorphous Oxide Semiconductor Memory Using High-k Charge Trap Layer

Amorphous oxide semiconductor memory devices with HfInZnOx as the channel layer and high k dielectric stacks as the charge storage medium were fabricated. HfO2 and Al2O3 and HfAlOx films were examined as the charge trap layers. The drain current - gate voltage transfer curves of the fabricated charge trap memories show a large hysteresis due to the electron trapping and de-trapping at the interfaces between the high-k charge storage layer and the SiO2. The device structure and operational scheme for the amorphous oxide semiconductor charge trap memories were suggested based on these properties.

LOW VOLTAGE SOI CMOS IMAGE SENSOR WITH PINNED PHOTODIODE ON HANDLE WAFER

We have fabricated 32 × 32 SOI CMOS active pixel image sensor with pinned photodiode on handle wafer in order to reduce dark current, transfer charge completely, and improve spectral response. The four transistor type active pixel image sensor is comprised of reset and source follower transistors on SOI seed wafer, while the pinned photodiode, transfer gate, and floating diffusion are fabricated on SOI handle wafer. The pinned photodiode could be optimized because the process of the photodiode on SOI handle wafer is independent of the transistor process on SOI seed wafer. The optimized pinned photodiode is simulated in order to understand complete charge transfer at 3.3 V and 2.5 V of transfer gate voltage, respectively. We also investigated the optical response of fabricated active pixel image sensor under different illumination density conditions from He - Ne laser source at 3.3 V and 2.5 V of transfer gate voltage.

Ferroelectric Pb(Zr0.52Ti0.48)/SiC field-effect transistor

Nonvolatile operation of ferroelectric gate field-effect transistors in silicon carbide (SiC) is demonstrated. Depletion mode transistors have been realized by forming a Pb(Zr0.52Ti0.48)O3/Al2O3 gate stack on n-type epitaxial channel layer and p-type substrate of 4H-SiC. A memory window, as wide as 5 V, has been observed in the drain current and the ferroelectric gate voltage transfer characteristics. The transistor showed memory effect from room temperature up to 200 °C, whereas stable transistor operation was observed up to 300 °C. The retention of remnant polarization was preserved after 2×104 s at 150 °C with no bias on the gate.

A review of recent MOSFET threshold voltage extraction methods

The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted from either measured drain current or capacitance characteristics, using a single or more transistors. Practical circuits based on some of the most common methods are available to automatically and quickly measure the threshold voltage. This article reviews and assesses several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics. The assessment focuses specially on single-crystal bulk MOSFETs. It includes 11 different methods that use the transfer characteristics measured under linear regime operation conditions. Additionally two methods for threshold voltage extraction under saturation conditions and one specifically suitable for non-crystalline thin film MOSFETs are also included. Practical implementation of the several methods presented is illustrated and their performances are compared under the same challenging conditions: the measured characteristics of an enhancement-mode n-channel single-crystal silicon bulk MOSFET with state-of-the-art short-channel length, and an experimental n-channel a-Si:H thin film MOSFET.

Short pulse transfer characteristics of Al/sub x/Ga/sub 1-x/As/GaAs and Al/sub x/Ga/sub 1-x/As/In/sub y/Ga/sub 1-y/As modulation-doped heterojunction FET's

Short-pulse drain current versus gate voltage transfer characteristics measured for modulation-doped HFETs (MODFETs) with four donor-layer-channel-layer combinations-(1) Al/sub 0.3/Ga/sub 0.7/As-GaAs, (2) Al/sub 0.2/Ga/sub 0.8/As-GaAs, (3) Al/sub 0.3/Ga/sub 0.7/As-In/sub 0.2/Ga/sub 0.8/As, and (4) Al/sub 0.2/Ga/sub 0.8/As-In/sub 0.2/ a/sub 0.8/As-are compared with the DC transfer characteristics. The measurements are relevant to high-speed switching in HFET circuits. Significant shifts in threshold voltage are observed between the DC and short-pulse characteristics for the structures with n/sup +/-Al/sub 0.3/Ga/sub 0.7/As donor layers, while the corresponding shifts for structures with n/sup +/-Al/sub 0.2/Ga/sub 0.8/As donor layers are relatively small or virtually nonexistent.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>