Transceiver Chipset Research Articles

A 39 GHz Dual-Channel Transceiver Chipset with an Advanced LTCC Package for 5G Multi-Beam MIMO Systems

A 39-GHz dual-channel CMOS transceiver chipset with an advanced LTCC packaging and the demonstration of a proposed dynamic multi-beam architecture based on the chipset for 5G MIMO applications. This article presents a 39 GHz transceiver front-end chipset for 5G multi-input multi-output (MIMO) applications. Each chip includes two variable-gain frequency-conversion channels and can support two simultaneous independent beams, and the chips also integrate a local-oscillator chain and digital module for multi-chip extension and gain-state control. To improve the radio-frequency performance, several circuit-level improvement techniques are proposed for the key building blocks in the front-end system. Furthermore, an advanced low-temperature co-fired ceramic process is developed to package the 39 GHz dual-channel transceiver chipset, and it achieves low packaging loss and high isolation between the two transmitting (TX)/receiving (RX) channels. Both the chip-level and system-in-package (SIP)-level measurements are conducted to demonstrate the performance of the transceiver chipset. The measurement characteristics show that the TX SIP provides 11 dB maximum gain and 10 dBm saturated output power, while the RX SIP achieves 52 dB maximum gain, 5.4 dB noise figure, and 7.2 dBm output 1 dB compression point. Single-channel communication link testing of the transceiver exhibits an error vector magnitude (EVM) of 3.72% and a spectral efficiency of 3.25 bit·s −1 ·Hz −1 for 64-quadrature amplitude modulation (QAM) modulation and an EVM of 3.76% and spectral efficiency of 3.9 bit·s −1 ·Hz −1 for 256-QAM modulation over a 1 m distance. Based on the chipset, a 39 GHz multi-beam prototype is also developed to perform the MIMO operation for 5G millimetre wave applications. The over-the-air communication link for one- and two-stream transmission indicates that the multi-beam prototype can cover a 5–150 m distance with comparable throughput.

A 112 Gb/s Radiation-Hardened Mid-Board Optical Transceiver in 130-nm SiGe BiCMOS for Intra-Satellite Links

We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises a vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for a flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130 nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/fMAX values of up to 250/340 GHz. Besides hardening by technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELTs) and digital logic cells. We report design features of the ICs and the module, and provide performance data from post-layout simulations. We present radiation evaluation data on analog devices and digital cells, which indicate that the transceiver ICs will reliably operate at typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites.

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS

This article presents the first 39-GHz phased-array transceiver (TRX) chipset for fifth-generation new radio (5G NR). The proposed transceiver chipset consists of 4 sub-array TRX elements with local-oscillator (LO) phase-shifting architecture and built-in calibration on phase and amplitude. The calibration scheme is proposed to alleviate phase and amplitude mismatch between each sub-array TRX element, especially for a large-array transceiver system in the base station (BS). Based on LO phase-shifting architecture, the transceiver has a 0.04-dB maximum gain variation over the 360° full tuning range, allowing constant-gain characteristic during phase calibration. A phase-to-digital converter (PDC) and a high-resolution phase-detection mechanism are proposed for highly accurate phase calibration. The built-in calibration has a measured accuracy of 0.08° rms phase error and 0.01-dB rms amplitude error. Moreover, a pseudo-single-balanced mixer is proposed for LO-feedthrough (LOFT) cancellation and sub-array TRX LO-to-LO isolation. The transceiver is fabricated in standard 65-nm CMOS technology with flip-chip packaging. The 8TX-8RX phased-array transceiver module 1-m OTA measurement supports 5G NR 400-MHz 256-QAM OFDMA modulation with -30.0-dB EVM. The 64-element transceiver has a EIRPMAX of 53 dBm. The four-element chip consumes a power of 1.5 W in the TX mode and 0.5 W in the RX mode.

A Fully Integrated 384-Element, 16-Tile, $W$ -Band Phased Array With Self-Alignment and Self-Test

This paper describes the design and implementation of a scalable $W$ -band phased-array system, with built-in self-alignment and self-test, based on an RFIC transceiver chipset manufactured in the TowerJazz 0.18- $\mu \text{m}$ SiGe BiCMOS technology with $f_{T}/f_{\text {MAX}}$ of 240/270 GHz. The RFIC integrates 24 phase-shifter elements (16TX/8RX or 8TX/16RX) as well as direct up- and down-converters, phase-locked loop with prime-ratio frequency multiplier, analog baseband, beam lookup memory, and diagnostic circuits for performance monitoring. Two organic printed circuit board (PCB) interposers with integrated antenna sub-arrays are designed and co-assembled with the RFIC chipsets to produce a scalable phased-array tile. Tiles are phase-aligned to one another through a daisy-chained local oscillator (LO) synchronization signal. Statistical analysis of the effects of LO misalignment between tiles on beam patterns is presented. Sixteen tiles are combined onto a carrier PCB to create a 384-element (256TX/128RX) phased-array system. A maximum saturated effective isotropic radiated power (EIRP) of 60 dBm (1 kW) is measured at boresight for the 256 transmit elements. Wireless links operating at 90.7 GHz using a 16-QAM constellation at a reduced EIRP of 52 dBm produced data rates beyond 10 Gb/s for an equivalent link distance in excess of 250 m.

A SiGe transceiver chipset for automotive radar applications using wideband modulation sequences

AbstractThis paper presents a W-band MIMO radar transceiver chipset for automotive applications, based on a Silicon Germanium technology. It consists of a reference VCO, operating at a center frequency of 38 GHz and a companion IC that comprises a complete millimeter-wave transceiver at 76 GHz. This chipset enables building multipurpose MIMO radar systems that can be scaled in terms of transmitter and receiver count. What makes this system innovative is the fact that it is able to handle more broadband signals than systems presented in current literature and is furthermore not limited to one modulation scheme. The chipset is capable of transmitting and receiving any signal waveform. The main goal of this work was to create a functional version of a VCO and a one-channel transceiver MMIC. Furthermore a demonstrator for a proof of concept was designed to test the MMICs on a system level. The realized VCO MMIC achieves a tuning frequency range of 6 GHz with a center frequency of 38 GHz and consumes 152 mW from a 3.3 V supply. The transceiver MMIC is fully functional and achieves a saturated output power of 11.5 dBm while drawing 670 mW from a 3.3 V supply.

A 10-Meter Active Optical Cable Utilizing POF With 4 × 10-Gb/s CMOS Transceiver Chipsets

This paper presents a 10-m active optical cable (AOC) utilizing a graded-index plastic optical fiber (POF) for HDMI applications, where 4-channel 10-Gb/s/ch transceiver chipsets were implemented in 0.13-μm CMOS process and integrated upon a FR4 PC-board within pluggable connectors. Passive optical alignment comprising optical devices, optical subassembly, and POF was precisely located within the tolerance range of +/-10 μm, leading to successful mass-production. The transmitter (Tx) includes a VCSEL driver exploiting equalization and feedforward pre-emphasis to support 10-Gb/s data modulation. Also, a novel input data detector is proposed to turn on/off VCSEL diodes automatically for longer sustainability and lower power consumption. The receiver (Rx) employs a double-gain feedforward transimpedance amplifier followed by a selectable two-stage equalizer to choose either 6-Gb/s or 10-Gb/s operations, depending upon the specified HDMI applications. Also, a simple dc offset current cancellation and a novel monitor circuit are proposed for stable biasing and to keep tracking the average photocurrent of each photodiode. Measured results of Tx demonstrate 5.6-mA bias currents and 6.0-mAPP modulation currents, consuming 21.25 mA in maximum, whereas Rx provides 56.7-dBΩ transimpedance gain, 6-GHz bandwidth, and -10.4-dBm optical sensitivity for 10 -12 BER with 21.2 mA current consumption. The 10-meter POF AOC demonstrates wide and clean eye-diagrams up to 10 Gb/s, successfully showing 8-Mpixel 60-fps video data stream.

A D-Band Multiplier-Based OOK Transceiver With Supplementary Transistor Modeling in 65-nm Bulk CMOS Technology

A D-band on–off keying (OOK) transceiver chipset is fabricated in a 65-nm bulk CMOS technology as a low-cost and highly integrative solution to short-distance wireless connectivity. Supplementary transistor modeling is performed for accurate circuit design at mm-wave frequencies. To overcome low transistor $\text{f}_{\mathrm {max}}$ and reduce dc power consumption, the transmitter employs a frequency-multiplier-based architecture with no power amplifier. The receiver adopts a non-coherent architecture consisting of a dc-coupled three-stage differential amplifier and an envelope detector. The OOK transmitter exhibits a measured output power of −9.8 dBm and an on–off level difference of 13.2 dB at 134.1 GHz. The receiver shows a measured average responsivity of 4.1 kV/W and a noise equivalent power of 211.4 pW/Hz1/2 over all D-band frequencies. The dc power consumption of the transmitter and the receiver is 76 and 32.5 mW, respectively. The transceiver is tested in both on-chip loopback and air-channel configurations and demonstrates data transmission up to 10 and 2 Gb/s at a distance of 0.03 m, respectively.

A 16-Element W-Band Phased-Array Transceiver Chipset With Flip-Chip PCB Integrated Antennas for Multi-Gigabit Wireless Data Links

This paper describes the design and implementation of a W-band phased-array system with printed circuit board (PCB) integrated antennas in two polarizations capable of multi-gigabit spectrally efficient wireless communication. The chipset is manufactured in a 0.18-μm SiGe BiCMOS technology with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> of 240-/270-GHz and is flip-chipped onto a lowcost organic PCB with integrated antenna arrays. Each chip is equipped with 16-transmit/4-receive or 16-receive/4-transmit calibrated phase shifter elements and direct upand downconverters plus a half-rate phase-locked loop. The different system tradeoffs required to establish a multi-Gb/s wireless link at millimeter waves are carefully studied. Built-in element failure detectors, power detectors, and digital interface enable factory calibration and self-test capability. Each transceiver chip operates from 1.5and 2.5-V supplies and consumes 5.5 and 4.5 W in transmit and receive mode, respectively. The peak transmitter effective isotropic radiation power is 34 dBm in each polarization with a measured receiver noise figure of 6.5 dB at 94 GHz. At a distance of 1 m, a maximum wireless data rate of 30 Gb/s (per polarization) using 64-QAM can be achieved and at 20 m, 8 Gb/s (dual polarization) can be established using QPSK modulation.

Real-Time 100 Gb/s NRZ and EDB Transmission With a GeSi Electroabsorption Modulator for Short-Reach Optical Interconnects

Transceivers based on electroabsorption modulators (EAM) are considered as a promising candidate for the next generation 400 GbE short-reach optical networks. They are capable of combining high bandwidth and low-power operation with a very compact layout, removing the need for traveling wave electrodes and dedicated 50 $\Omega$ termination. In this paper, we demonstrate the first silicon-based EAM, in combination with an in-house developed SiGe BiCMOS transceiver chipset, capable of transmitting single-lane 100 Gb/s non-return-to-zero in real-time. Transmission over 500 m of standard single mode fiber and 2 km of nonzero dispersion shifted fiber is demonstrated, assuming a forward-error coding scheme is used with a bit-error ratio limit of $3.8\times 10^{-3}$ . Due to the high line rate, transmission over longer fiber spans was limited by the chromatic distortion in the fiber. As a possible solution, electrical duobinary modulation is proposed as it is more resilient to this type of fiber distortion by reducing the required optical bandwidth. We show improved performance for longer fiber spans with a 100 Gb/s electrical duobinary link, resulting in real-time sub-forward error coding operation over more than 2 km of standard single-mode fiber without any digital signal processing. Finally, the possibility of a 100 Gb/s EAM-to-EAM link is investigated.

A Low-Power SiGe BiCMOS 190-GHz Transceiver Chipset With Demonstrated Data Rates up to 50 Gbit/s Using On-Chip Antennas

This paper presents a 190-GHz direct conversion transceiver (TRX) chipset with on-chip antennas implemented in a 130-nm SiGe BiCMOS technology for short-distance high-data-rate wireless links. The transmitter (TX) consists of an active fundamental upconversion mixer, a local oscillator (LO) driver, and a passive balun for differential to single-ended conversion of the RF signal. The receiver (RX) is composed of a low-noise amplifier, an active fundamental mixer, an LO driver, a variable-gain baseband (BB) amplifier, and a totem-pole output stage. The wireless communication between TX and RX is enabled by on-chip monopole antennas, which are fabricated using standard wire-bonding tools. Measurements of the TRX chipset equipped with these antennas show a 6-dB BB link bandwidth of 20 GHz, corresponding to 40 GHz of the RF link bandwidth. In a data transmission test setup based on a BPSK modulation, data rates of up to 40 Gbit/s over 20 mm and up to 50 Gbit/s over 6 mm are demonstrated. Consuming only 122 mW in the RX and 32 mW in the TX, this leads to a very low required energy per transferred bit of 3.9 and 3.1 pJ for the 40- and 50-Gbit/s link, respectively.

A 1.5 Gbps Transceiver Chipset in 0.13-mm CMOS for Serial Digital Interface

This paper presents a transceiver chipset realized in a 0.13-mm CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of 1.485 mm², whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of 1.44 mm².

A 100 MHz PRF IR-UWB CMOS Transceiver With Pulse Shaping Capabilities and Peak Voltage Detector

This paper presents a high-rate IR-UWB transceiver chipset implemented in a 130-nm CMOS technology for WBAN and biomedical applications in the 3.1–4.9 GHz band. The transmitter is based on a pulse synthesizer and an analytical up-converted Gaussian pulse is used to predict its settings. Its measured peak-to-peak output voltage is equal to $0.9~V_{\mathrm{ pp}}$ on a 100 $\Omega $ load for a central frequency of 4 GHz, and a supply voltage of 1.2 V, which gives an emitted energy per pulse of 0.64 pJ. The receiver is a non-coherent architecture based on an LNA followed by a peak-voltage detector. A BER of 10−3 is measured for a 3.1–4.9 GHz input peak-to-peak pulse amplitude of 1.1 mV, which corresponds to a sensitivity of −85.8 dBm at 1 Mb/s and gives a communication range estimated to 1.9 m.

95–105 GHz 352 mW All-Silicon Cavity-Coupled Pulsed Echo Rotational Spectroscopy System in 65 nm CMOS

A new CMOS-based spectroscopy instrument for in situ rotational spectroscopy of gases in space is presented. The design is based on the pulsed Fourier transform method of Balle–Flygare but operates at mm-wave frequencies as oppose to traditional microwave implementations. The core of the instrument consists of a 65 nm CMOS transceiver chipset with integrated mixers, synthesizers, and amplifiers covering the 95–105 GHz frequency band. The CMOS chips are coupled with a semiconfocal cavity which builds field strength for pumping rotational transitions. Details of the CMOS chip design as well as system level testing are discussed.

ALICE inner tracking system readout electronics prototype testing with the CERN ``Giga Bit Transceiver''

The ALICE Collaboration is preparing a major detector upgrade for the LHC Run 3, which includes the construction of a new silicon pixel based Inner Tracking System (ITS). The ITS readout system consists of 192 readout boards to control the sensors and their power system, receive triggers, and deliver sensor data to the DAQ. To prototype various aspects of this readout system, an FPGA based carrier board and an associated FMC daughter card containing the CERN Gigabit Transceiver (GBT) chipset have been developed. This contribution describes laboratory and radiation testing results with this prototype board set.

Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications

Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

High rate UWB CMOS transceiver chipset for WBAN and biomedical applications

This work presents a high rate UWB transceiver chipset implemented in a 130 nm CMOS technology for WBAN and biomedical applications in the 3–5 GHz band. The transmitter architecture is based on a double-filter excitation technique that can generate high magnitude pulses and address bipolar modulations such as BPSK. Measurements show that bipolar pulses with a peak-to-peak voltage of 1.9 Vpp for a power consumption of 139 µW@100 kbps can be generated. The receiver is a non-coherent architecture based on LNA followed by an envelope detector. A BER of 10−3 is achieved for a 3–5 GHz input peak-to-peak amplitude of 3.4 mVpp which corresponds to a −89.3 dBm sensitivity at 100 kbps. The energy consumption of the receiver and of the transmitter is respectively 0.144 nJ/bit and 196 pJ/bit at 100 Mbps. To improve the budget link of our non-coherent based transceiver a Randomly Alternate OOK signaling is proposed which leads to an estimated communication range of 2.36 m in a free space propagation channel.

A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage

This paper presents a fully integrated transceiver chipset based on the WiGig/IEEE 802.11ad standard targeting mobile usage. The chipset is developed for single-carrier (SC) modulation, which is suitable for reduced power consumption. However, the SC modulation is sensitive to in-band amplitude variations, mainly made worse by the gain variations of analog circuits and multipath delay spread. In order to compensate for these gain variations, the proposed chipset employs built-in TX in-band calibration and an RX frequency domain equalizer (FDE). The proposed techniques relax the requirement for high speed analog circuits, leading to less power consumption while minimizing the increase of hardware size. The test chip achieves 1.8 Gb/s MAC throughput for up to 40 cm and 1.5 Gb/s for up to 1 m while consuming 788 mW in TX and 984 mW in RX mode.

Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”

The authors made an error in Fig. 19 in the above-named article [ibid., vol. 47, no. 12, pp. 3160–3171, Dec. 2012]. The figure is the same as Fig. 13 by mistake. The correct figure "Data rate/throughput measurement setup" is shown here. The authors apologize for any confusion.

A 1µs Settling Time Fully Digital AGC System with a 1GHz-Bandwidth Variable Gain Amplifier for WiGig/IEEE802.11ad Multi-Gigabit Wireless Transceivers

This paper presents an automatic gain control (AGC) system suitable for 60GHz direct conversion receivers. By using a two step gain control algorithm with high-pass filter cutoff frequency switching, the proposed AGC system realizes fast settling time and wide dynamic range simultaneously. The paper also discusses wide-bandwidth variable gain amplifier (VGA) design. By introducing digitally-controlled resistors and gain flattening capacitors, the proposed VGA realizes wide gain range while compensating gain variations due to parasitic capacitance of MOS switches. The AGC system is implemented in a transceiver chipset where RFIC and BBIC are fabricated in 90nm CMOS and 40nm CMOS respectively. The measurement shows excellent dynamic range of 47dB with +/-1dB gain accuracy within 1µs settling time, which satisfies the stringent requirements of the IEEE802.11ad standard.

The GBLD: a radiation tolerant laser driver for high energy physics applications

The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC which is part of the GigaBit Transceiver (GBT) chipset. It is aimed to drive both edge emitting and VCSEL laser diodes at a data rate in excess of 5 Gb/s. The GBLD can provide a modulation current up to 24 mA and a bias current up to 43 mA. Pre- and de-emphasis functions are implemented to compensate for high external capacitive loads and asymmetric laser response. The chip is designed in a 130 nm CMOS technology and is powered by a single 2.5 V supply.