Abstract
The ALICE Collaboration is preparing a major detector upgrade for the LHC Run 3, which includes the construction of a new silicon pixel based Inner Tracking System (ITS). The ITS readout system consists of 192 readout boards to control the sensors and their power system, receive triggers, and deliver sensor data to the DAQ. To prototype various aspects of this readout system, an FPGA based carrier board and an associated FMC daughter card containing the CERN Gigabit Transceiver (GBT) chipset have been developed. This contribution describes laboratory and radiation testing results with this prototype board set.
Highlights
This content has been downloaded from IOPscience
: The ALICE Collaboration is preparing a major detector upgrade for the LHC Run 3, which includes the construction of a new silicon pixel based Inner Tracking System (ITS)
The design of the Readout Unit (RU) consists of an FPGA to handle the data collection and formatting, as well as the control of the sensors, and a radiation-hard fiber-optic transmission chipset, the “Gigabit Transceiver Optical Link” (GBT) developed by the GBT collaboration for the LHC experiment upgrades [4, 5]
Summary
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2016 JINST 11 C12074 (http://iopscience.iop.org/1748-0221/11/12/C12074) View the table of contents for this issue, or go to the journal homepage for more Download details: IP Address: 128.141.192.151 This content was downloaded on 21/03/2017 at 12:44 Please note that terms and conditions apply. To prototype various aspects of this readout system, an FPGA based carrier board and an associated FMC daughter card containing the CERN
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