Traditional CPU Research Articles

Accelerating multimodal gravitational waveforms from precessing compact binaries with artificial neural networks

Gravitational waves from the coalescences of black hole and neutron stars afford us the unique opportunity to determine the sources' properties, such as their masses and spins, with unprecedented accuracy. To do so, however, theoretical models of the emitted signal that are i) extremely accurate and ii) computationally highly efficient are necessary. The inclusion of more detailed physics such as higher-order multipoles and relativistic spin-induced orbital precession increases the complexity and hence also computational cost of waveform models, which presents a severe bottleneck to the parameter inference problem. A popular method to generate waveforms more efficiently is to build a fast surrogate model of a slower one. In this paper, we show that traditional surrogate modelling methods combined with artificial neural networks can be used to build a computationally highly efficient while still accurate emulation of multipolar time-domain waveform models of precessing binary black holes. We apply this method to the state-of-the-art waveform model SEOBNRv4PHM and find significant computational improvements: On a traditional CPU, the typical generation of a single waveform using our neural network surrogate SEOBNN_v4PHM_4dq2 takes 18ms for a binary black hole with a total mass of $44 M_{\odot}$ when generated from 20Hz. In comparison to SEOBNRv4PHM itself, this amounts to an improvement in computational efficiency by two orders of magnitude. Utilising additional GPU acceleration, we find that this speed-up can be increased further with the generation of batches of waveforms simultaneously. Even without additional GPU acceleration, this dramatic decrease in waveform generation cost can reduce the inference timescale from weeks to hours.

Enabling PIM-based AES encryption for online video streaming

Encryption of streaming video is becoming critical to the success of commercial enterprise and to consumers alike. To meet copyright and privacy requirements, encrypting video data on-the-fly during transmission is necessary. In this work we employ Advanced Encryption Standard (AES) due to its security and flexibility. However, it is compute and memory-intensive. Increasing the number of concurrent streamers only exacerbates the problem. To ameliorate this situation, we propose a Processing-In Memory (PIM) architecture AESPIM to offload AES encryption computation to the memory side. Based on our experimental results, AES performance can be improved up to 42% with compared with the traditional CPU based implementation by significantly reducing data movement and increased memory bandwidth. We further study the data-level and user-level parallelism of the video streaming environment in our base design AESPIM architecture, and propose an advanced design based on user-level parallelism to achieve additional 34% performance improvement. Furthermore, we implement a QoS-aware scheduler to solve its potential workload imbalance bottleneck. Based on evaluation results, performance can be further optimized by up to 6% on average.

LiteCON : An All-photonic Neuromorphic Accelerator for Energy-efficient Deep Learning

Deep learning is highly pervasive in today's data-intensive era. In particular, convolutional neural networks (CNNs) are being widely adopted in a variety of fields for superior accuracy. However, computing deep CNNs on traditional CPUs and GPUs brings several performance and energy pitfalls. Several novel approaches based on ASIC, FPGA, and resistive-memory devices have been recently demonstrated with promising results. Most of them target only the inference (testing) phase of deep learning. There have been very limited attempts to design a full-fledged deep learning accelerator capable of both training and inference. It is due to the highly compute- and memory-intensive nature of the training phase. In this article, we propose LiteCON , a novel analog photonics CNN accelerator. LiteCON uses silicon microdisk-based convolution, memristor-based memory, and dense-wavelength-division-multiplexing for energy-efficient and ultrafast deep learning. We evaluate LiteCON using a commercial CAD framework (IPKISS) on deep learning benchmark models including LeNet and VGG-Net. Compared to the state of the art, LiteCON improves the CNN throughput, energy efficiency, and computational efficiency by up to 32×, 37×, and 5×, respectively, with trivial accuracy degradation.

A Dynamic Multitarget Detection Algorithm in front of Vehicle Based on Embedded System and Internet of Things

There are few studies for the classification detection and dynamic multitarget detection of the targets in front of vehicles. In order to solve this problem, a dynamic multitarget detection algorithm is proposed. First, a dynamic multitarget detection with displacement at any time is suggested; secondly, a multitarget detection algorithm based on improved You Only Look Once version 3 (YOLOv3) is proposed for the detection of multitarget high probability risk events in front of the vehicle. The YOLOv3 algorithm model is a lightweight backbone network that uses embedded real-time detection technologies. In this paper, we use a lightweight Mobilenetv2 to replace Darknet-53 for feature extraction. Moreover, an optimizer is used for multiobjective feature extraction, group normalization, and multiobjective feature extraction. The results show that in comparison with the original YOLOv3 algorithm, the detection leakage rate of the improved YOLOv3 multitarget detection algorithm is less than 5%, and the amount of model parameters in this paper is reduced by 95% as compared to the traditional data and CPU intertime is reduced to 78%.

Cognitively reconfigurable mimic-based heterogeneous password recovery system

The recovery of encrypted information systems based on password verification mechanisms is an important task in electronic forensics, data restoration, illegal information filtering, and network security maintenance. The traditional password recovery system is mainly based on CPUs and GPUs, which have low cracking efficiency and cannot meet the computing needs of users. Therefore, this paper proposes a cognitively reconfigurable mimic-based heterogeneous password recovery system. Applying the concept of mimic computing, a multidimensional and reconfigurable hybrid heterogeneous system is established through the use of CPUs, GPUs, and FPGAs, which works by coordinating software and hardware to improve the system’s computing ability and range of solution types to meet diverse cracking needs. Second, high-performance password recovery and password generation algorithms that run on FPGAs are designed to expedite the calculation and verification of passwords. Third, a hierarchical password database is established to realize dynamic feedback and updating of passwords, aiming for various application scenarios and improving password recovery efficiency. Finally, through task perception and decision-making reasoning and with dynamic structural transformation and load balancing, the computing potential of the system is fully mobilized so that the entire system can efficiently complete the encryption recovery task. Experimental analysis and results show that compared with traditional CPU and GPU systems, our system exhibits significantly improved recovery efficiency and can better support heterogeneous systems, with high scalability and energy efficiency.

Lean Neural Networks for Autonomous Radar Waveform Design.

In recent years, neural networks have exploded in popularity, revolutionizing the domains of computer vision, natural language processing, and autonomous systems. This is due to neural networks ability to approximate complex non-linear functions. Despite their effectiveness, they generally require large labeled data sets and considerable processing power for both training and prediction. Some of these bottlenecks have been mitigated by recent increased availability of high-quality data sets, improvements in neural network development software, and greater hardware support. Due to algorithmic bloat, neural network inference times and imprecision make them undesirable for some problems where fast classical algorithm solutions already exist, other classes of algorithms, such as convex optimization, with non-trivial execution times could be reduced using neural solutions. These algorithms could be replaced with light-weight neural networks, benefiting from their high degree of parallelization and high accuracy when properly trained. Previous work has explored how low size, weight, and power (low SWaP) neural networks and neuromorphic computing can be used to improve autonomous radar waveform design techniques that currently rely on convex optimization. Autonomous radar waveform design helps meet the need for interference mitigation caused by an ever-growing number of consumer and commercial technologies which pollute the radio frequency (RF) spectrum. Spectral notching, a radar waveform design technique, augments transmitted radar waveforms to avoid frequencies with excessive interference while maintaining the integrity of the waveform. In this paper, we extend that work, demonstrating that lean neural networks and specialized hardware can improve inference time for waveform design without sacrificing accuracy. Our lean neural solution incorporates problem-specific information into the layer structures and loss functions to decrease network size and improve accuracy. We provide model outcomes implemented on radio frequency system on a chip (RFSoC) hardware that support our simulation results. Our neural network solution decreases inference time on traditional CPU hardware by 1057× and on GPU hardware accelerators by 883× while maintaining 99% cosine similarity.

Accelerating CFD simulation with high order finite difference method on curvilinear coordinates for modern GPU clusters

A high fidelity flow simulation for complex geometries for high Reynolds number (Re) flow is still very challenging, requiring a more powerful HPC system. However, the development of HPC with traditional CPU architecture suffers bottlenecks due to its high power consumption and technical difficulties. Heterogeneous architecture computation is raised to be a promising solution to the challenges of HPC development. GPU accelerating technology has been utilized in low order scheme CFD solvers on the structured grid and high order scheme solvers on unstructured meshes. The high-order finite difference methods on structured grids possess many advantages, e.g., high efficiency, robustness, and low storage. However, the strong dependence among points for a high-order finite difference scheme still limits its application on the GPU platform. In the present work, we propose a set of hardware-aware technology to optimize data transfer efficiency between CPU and GPU, as well as communication efficiency among GPUs. An in-house multi-block structured CFD solver with high order finite difference methods on curvilinear coordinates is ported onto the GPU platform and obtains satisfying performance with a speedup maximum of around 2000x over a single CPU core. This work provides an efficient solution to apply GPU computing in CFD simulation with specific high order finite difference methods on current GPU heterogeneous computers. The test shows that significant accelerating effects can be achieved for different GPUs.

Metrics and Design of an Instruction Roofline Model for AMD GPUs

Due to the recent announcement of the Frontier supercomputer, many scientific application developers are working to make their applications compatible with AMD (CPU-GPU) architectures, which means moving away from the traditional CPU and NVIDIA-GPU systems. Due to the current limitations of profiling tools for AMD GPUs, this shift leaves a void in how to measure application performance on AMD GPUs. In this article, we design an instruction roofline model for AMD GPUs using AMD’s ROCProfiler and a benchmarking tool, BabelStream (the HIP implementation), as a way to measure an application’s performance in instructions and memory transactions on new AMD hardware. Specifically, we create instruction roofline models for a case study scientific application, PIConGPU, an open source particle-in-cell simulations application used for plasma and laser-plasma physics on the NVIDIA V100, AMD Radeon Instinct MI60, and AMD Instinct MI100 GPUs. When looking at the performance of multiple kernels of interest in PIConGPU we find that although the AMD MI100 GPU achieves a similar, or better, execution time compared to the NVIDIA V100 GPU, profiling tool differences make comparing performance of these two architectures hard. When looking at execution time, GIPS, and instruction intensity, the AMD MI60 achieves the worst performance out of the three GPUs used in this work.

EOS: Atmospheric Radiative Transfer in Habitable Worlds with HELIOS

Abstract We present EOS, a procedure for determining the outgoing longwave radiation (OLR) and top-of-atmosphere (TOA) albedo for a wide range of conditions expected to be present in the atmospheres of rocky planets with temperate conditions. EOS is based on HELIOS and HELIOS-K, which are novel and publicly available atmospheric radiative transfer (RT) codes optimized for fast calculations with GPU processors. These codes were originally developed for the study of giant planets. In this paper we present an adaptation for applications to terrestrial-type, habitable planets, adding specific physical recipes for the gas opacity and vertical structure of the atmosphere. To test the reliability of the procedure, we assessed the impact of changing line opacity profile, continuum opacity model, atmospheric lapse rate, and tropopause position prescriptions on the OLR and the TOA albedo. The results obtained with EOS are in line with those of other RT codes running on traditional CPU processors, while being at least one order of magnitude faster. The adoption of OLR and TOA albedo data generated with EOS in a zonal and seasonal climate model correctly reproduces the fluxes of the present-day Earth measured by the CERES spacecraft. The results of this study disclose the possibility to incorporate fast RT calculations in climate models aimed at characterizing the atmospheres of habitable exoplanets.

HARMS: A Hardware Acceleration Architecture for Real-Time Event-Based Optical Flow

Event-based vision sensors produce asynchronous event streams with high temporal resolution based on changes in the visual scene. The properties of these sensors allow for accurate and fast calculation of optical flow as events are generated. Existing solutions for calculating optical flow from event data either fail to capture the true direction of motion due to the aperture problem, do not use the high temporal resolution of the sensor, or are too computationally expensive to be run in real time on embedded platforms. In this research, we first present a faster version of our previous algorithm, ARMS (Aperture Robust Multi-Scale flow). The new optimized software version (fARMS) significantly improves throughput on a traditional CPU. Further, we present hARMS, a hardware realization of the fARMS algorithm allowing for real-time computation of true flow on low-power, embedded platforms. The proposed hARMS architecture targets hybrid system-on-chip devices and was designed to maximize configurability and throughput. The hardware architecture and fARMS algorithm were developed with asynchronous neuromorphic processing in mind, abandoning the common use of an event frame and instead operating using only a small history of relevant events, allowing latency to scale independently of the sensor resolution. This change in processing paradigm improved the estimation of flow directions by up to 73% compared to the existing method and yielded a demonstrated hARMS throughput of up to 1.21 Mevent/s on the benchmark configuration selected. This throughput enables real-time performance and makes it the fastest known realization of aperture-robust, event-based optical flow to date.

Research on Programming Model and Compilation Optimization Technology of Multi-Core GPU

GPGPU (General Purpose Computing on Graphics Processing Units) has been widely applied to high performance computing. However, GPU architecture and programming model are different from that of traditional CPU. Accordingly, it is rather challenging to develop efficient GPU applications. This paper focuses on the key techniques of programming model and compiler optimization for many-core GPU, and addresses a number of key theoretical and technical issues. This paper proposes a many-threaded programming model ab-Stream, which would transparentize architecture differences and provide an easy to parallel, easy to program, easy to extend and easy to tune programming model. In addition, this paper proposes memory optimization and data transfer transformation according to data classification. Firstly, this paper proposes data layout pruning based on classification memory, and then proposes Ta T (Transfer after Transformed) for transferring Strided data between CPU and GPU. Experimental results demonstrate that proposed techniques would significantly improve performance for GPGPU applications.

A Software Development Kit and Translation Layer for Executing Intel 8080 Assembler on a Quantum Computer (August 2022)

One of the major obstacles to the adoption of quantum computing is the requirement to define quantum circuits at the quantum gate level. Many programmers are familiar with high-level or low-level programming languages but not quantum gates nor the low-level quantum logic required to derive useful results from quantum computers. The steep learning curve involved when progressing from quantum gates to complex simulations such as Shor's algorithm has proven too much for many developers. The purpose of this paper and the software presented within, addresses this challenge by providing a Software Development Kit (SDK), translation layer, emulator and a framework of techniques for executing Intel 8080/Z80 assembler on a quantum computer, i.e. all salient points of CPU execution, logic, arithmetic and bitwise manipulation will be executed on the quantum computer using quantum circuits. This provides a novel means of displaying the equivalency and interoperability of quantum and classical computers. Developers and researchers can use the SDK to write code in Intel 8080/Z80 assembler which is executed locally via traditional emulation and remotely on a quantum computer in parallel. The emulator features side-by-side code execution with visibility of the running quantum circuit and re-usable/overridable methods. This enables programmers to learn, reuse and contrast techniques for performing any traditional CPU based technique/instruction on a quantum computer; e.g. a programmer may know how to multiply and perform checks on a classical CPU but is not able to perform the same tasks in a quantum implementation, this SDK allows the programmer to pick and choose the methods they would like to use to fulfil their requirements. The SDK makes use of open-source software, specifically Python and Qiskit for the emulation, translation, API calls and execution of user supplied code or binaries.

An Efficient GPU Implementation of a Coupled Overland-Sewer Hydraulic Model with Pollutant Transport

Numerical simulation of flows that consider interaction between overland and drainage networks has become a practical tool to prevent and mitigate flood situations in urban environments, especially when dealing with intense storm events, where the limited capacity of the sewer systems can be a trigger for flooding. Additionally, in order to prevent any kind of pollutant dispersion through the drainage network, it is very interesting to have a certain monitorization or control over the quality of the water that flows in both domains. In this sense, the addition of a pollutant transport component to both surface and sewer hydraulic models would benefit the global analysis of the combined water flow. On the other hand, when considering a realistic large domain with complex topography or streets structure, a fine spatial discretization is mandatory. Hence the number of grid cells is usually very large and, therefore, it is necessary to use parallelization techniques for the calculation, the use of Graphic Processing Units (GPU) being one of the most efficient due to the leveraging of thousands of processors within a single device. In this work, an efficient GPU-based 2D shallow water flow solver (RiverFlow2D-GPU) is fully coupled with EPA’s Storm Water Management Model (SWMM). Both models are able to develop a transient water quality analysis taking into account several pollutants. The coupled model, referred to as RiverFlow2D-GPU UD (Urban Drainge) is applied to three real-world cases, covering the most common hydraulic situations in urban hydrology/hydraulics. A UK Environmental Agency test case is used as model validation, showing a good agreement between RiverFlow2D-GPU UD and the rest of the numerical models considered. The efficiency of the model is proven in two more complex domains, leading to a >100x faster simulations compared with the traditional CPU computation.

Reconfigurable and High-Efficiency Password Recovery Algorithms Based on HRCA

Cryptographic algorithms are widely used in information security fields such as network protocol authentication and commercial encryption software. Password recovery based on the hash algorithm is an important means of electronic forensics, encrypted information restoration, illegal information filtering, and network security maintenance. The traditional password recovery system is based mainly on the CPU and GPU and has a low energy efficiency ratio and cracking efficiency and cannot meet high-performance computing requirements. To further improve the computational efficiency and application flexibility of password recovery algorithms, this paper proposes a reconfigurable computing kernel design method based on a hybrid reconfigurable computing array (HRCA). Through in-depth analysis of the hash algorithm, the basic computing kernel set is extracted, and the combination design is carried out from the unit kernel, interconnection and storage structure to reconstruct the hash algorithm to match the application with the appropriate structure. Second, combined with the pipeline technology, the full pipeline hash and high-speed password attack algorithms are optimized and implemented to meet the needs of high-performance computing. Finally, an advanced computing kernel library is established, and the combination of a computing kernel map from the control and communication levels to achieve multidimensional reconfigurable computing and an overall placement strategy is used to make full use of the chip resources to improve computational efficiency. The experimental results and analysis show that compared with traditional CPU and GPU methods, the password recovery algorithm designed in this paper has the highest cracking speeds at 78.22 times and 2.65 times that of the CPU and GPU, respectively, and the highest energy efficiency ratio is 25.88 times and 3.16 times that of the CPU and GPU, respectively. Furthermore, the recovery efficiency has been significantly improved and meets the requirements of high-performance password recovery computing.

Usage of GPUs in ALICE Online and Offline processing during LHC Run 3

ALICE will significantly increase its Pb–Pb data taking rate from the 1 kHz of triggered readout in Run 2 to 50 kHz of continuous readout for LHC Run 3. Updated tracking detectors are installed for Run 3 and a new twophase computing strategy is employed. In the first synchronous phase during the data taking, the raw data is compressed for storage to an on-site disk buffer and the required data for the detector calibration is collected. In the second asynchronous phase the compressed raw data is reprocessed using the final calibration to produce the final reconstruction output. Traditional CPUs are unable to cope with the huge data rate and processing demands of the synchronous phase, therefore ALICE employs GPUs to speed up the processing. Since the online computing farm performs a part of the asynchronous processing when there is no beam in the LHC, ALICE plans to use the GPUs also for this second phase. This paper gives an overview of the GPU processing in the synchronous phase, the full system test to validate the reference GPU architecture, and the prospects for the GPU usage in the asynchronous phase.

Rapid Topology Generation and Core Mapping of Optical Network-on-Chip for Heterogeneous Computing Platform

The explosive growth of deep learning (DL)–based artificial intelligence (AI) applications necessitates extraordinary computing capabilities that cannot be achieved using traditional CPU standalone computing. Therefore, the heavy mission-critical DL kernel computing currently relies on a heterogeneous computing (HGC) platform integrated with CPUs, GPUs, and accelerators, as well as substantial data storage elements. However, the metallic electrical interconnection in the existing manycore platform would not be sustainable for handling the massively increasing bandwidth demand of big data driven AI applications. Incorporating an optical network-on-chip (ONoC) for providing ultrahigh bandwidth, we propose a rapid topology generation and core mapping of ONoC (REGO) for energy-efficient HGC multicore architecture. The genetic algorithm (GA)-based REGO utilizes the structural characteristics of the optical router to the fitness function and thus compromises the trade-off between the required throughput, optical signal-to-noise ratio (OSNR), and total energy consumption. Furthermore, the crossover step accelerates the convergence speed by suppressing randomness in the GA, thus significantly reducing excessive running time owing to the NP-hard property. The generated ONoC through REGO demonstrates, on an average, an increase of 63.29 % and 22.80 % in throughput and a decrease of 50.24 % and 9.56 % in energy per bit, in the VGG-16 and VGG-19 compared with the conventional mesh- and torus-topology-based ONoCs, respectively.

Asymmetric regular sampling SPWM method based on tangent approximation algorithm

Objectives In order to improve the quality of sinusoidal waveform output by the ship's high-frequency inverter charging device and reduce the CPU occupancy rate, an asymmetric regular sampling sinusoidal pulse width modulation (SPWM) method based on tangent approximation is proposed. Methods According to the basic principle and calculation method of the asymmetric regular sampling SPWM method based on tangent approximation, a Matlab/Simulink simulation model is built, and then the software algorithm flow that can be used in the high-frequency inverter charging device is designed together with the actual output of the tangent approximation method. The effects are then compared and verified by experiments. Results The simulation results show that under pure resistive load and resistive inductive load, the total harmonic distortion (THD) of the load-end waveform based on tangent approximation method is 2.12% and 2.08%, respectively, and its waveform quality is better than symmetric regular sampling. The experimental results show that the THD of load-end waveform based on the tangent approximation method is significantly lower than the symmetric regular sampling method. When the effective value of the input line voltage is 580 V (the modulation ratio is 0.8), the quality of the output waveform is relatively optimal. Conclusions The asymmetric regular sampling SPWM method based on tangent approximation overcomes the shortcomings of the traditional symmetric regular sampling method, such as the low quality of the output waveform and the traditional asymmetric regular sampling method's high sampling frequency and high CPU occupancy rate. The research results can provide reference for the design of ship's high frequency inverter charging devices.

Experimental investigation of the thermal performance of a heat sink with U-shaped heat pipes

To meet the urgent requirement of high heat flux cooling of the chips in current electronic equipment, a unique and reliable U-shaped heat pipe bonded heat sink was developed and experimentally investigated for CPU cooling in computers. This novel heat sink was bonded with air-cooled fin stacks and two U-shaped heat pipes through the base plate. In this work, the effects of relevant parameters, including orientation of the heat sink, working conditions (air velocity and ambient temperature) of the computer on the variation of CPU temperature and overall thermal resistance of the heat sink are considered. The tests indicate that the overall thermal resistance of the heat sink at orientation α = 90° is lower than that in another five orientation cases, and reaches the minimum value of 0.263 °C/W. If the operating temperature of the CPU is limited to below 70 °C, the maximum heat dissipation power of the heat sink reaches 130 W. It can be seen that the orientation and working conditions of the heat sink have significant effects on the cooling capacity which results in variation in the overall thermal resistance of the heat sink. In addition, the comparison of overall thermal resistance between the novel heat sink and a traditional CPU fin-bonded heat sink indicates that the novel heat sink provides greater reliability.

Analysis of differential distribution of lightweight block cipher based on parallel processing on GPU

As the fast development of IoT technology, various security solutions have to be considered when the corresponding solutions are being deployed. Due to the lightweight nature of the IoT devices such as the RFID tags and so on, traditional encryption schemes such as AES which are relatively heavy in the sense of operations cannot be applied here. Lightweight block ciphers have since become a default standard when considering security protections on such lightweight IoT devices. Compared with the security analysis approaches by taking advantage of the differential or linear cryptanalysis, the security margin of lightweight block ciphers can be further derived more accurately due to the small internal state. In this paper, we investigate the security margin of the lightweight block cipher structure especially the SPN design by taking advantage of the parallel computing power of modern GPU architecture. We show how to accelerate the computing of the statistical distinguisher, which is the crucial point for analyzing the security of the cipher design. Our proposed methods gain notable advantage against traditional CPU architecture in terms of time complexity and possess extensibility for other block ciphers.

Reviewing the Computational Performance of Structured and Unstructured Grid Deterministic SN Transport Sweeps on Many-Core Architectures

In recent years the computer processors underpinning the large, distributed, workhorse computers used to solve the Boltzmann transport equation have become ever more parallel and diverse. Traditional CPU architectures have increased in core count, reduced in clock speed and gained a deep memory hierarchy. Multiple processor vendors offer a collectively diverse range of both CPUs and GPUs, with the architectures used in the fastest machines in the world ever growing in diversity of many-core architectures. Going forward, the landscape of processor technologies will require our codes to function well across multiple architectures. This ever increasing range of architectures represents a unique challenge for solving the Boltzmann equation using deterministic methods in particular, and so it is important to characterize the performance of those key algorithms across the processor spectrum. The solution of the transport equation is computationally expensive, and so we require well optimized and highly parallel solver implementations in order to solve interesting problems quickly. In this work we explore the performance profiles of deterministic SN transport sweeps for both 3D structured (Cartesian) and unstructured (hexahedral) meshes. The study focuses on the characteristics of computational performance which are responsible for the actual performance of a transport solver.