On-chip Cache Research Articles

Triangle Dropping: An Occluded-geometry Predictor for Energy-efficient Mobile GPUs

This article proposes a novel micro-architecture approach for mobile GPUs aimed at early removing the occluded geometry in a scene by leveraging frame-to-frame coherence, thus reducing the overall energy consumption. Mobile GPUs commonly implement a Tile-Based Rendering (TBR) architecture that differentiates two main phases: the Geometry Pipeline , where all the geometry of a scene is processed; and the Raster Pipeline , where primitives are rendered in a framebuffer. After the Geometry Pipeline, only non-culled primitives inside the camera’s frustum are stored into the Parameter Buffer , a data structure stored in DRAM. However, among the non-culled primitives there is a significant amount that are rendered but non-visible at all , resulting in useless computations. On average, 60% of those primitives are completely occluded in our benchmarks. Despite TBR architectures use on-chip caches for the Parameter Buffer, about 46% of the DRAM traffic still comes from accesses to such buffer. The proposed Triangle Dropping technique leverages the visibility information computed along the Raster Pipeline to predict the primitives’ visibility in the next frame to early discard those that will be totally occluded, drastically reducing Parameter Buffer accesses. On average, our approach achieves overall 14.5% energy savings, 28.2% energy-delay product savings, and a speedup of 20.2%.

The full story of 1000 cores

In our initial DaMoN paper, we set out the goal to revisit the results of “Starring into the Abyss [...] of Concurrency Control with [1000] Cores” (Yu in Proc. VLDB Endow 8: 209-220, 2014). Against their assumption, today we do not see single-socket CPUs with 1000 cores. Instead, multi-socket hardware is prevalent today and in fact offers over 1000 cores. Hence, we evaluated concurrency control (CC) schemes on a real (Intel-based) multi-socket platform. To our surprise, we made interesting findings opposing results of the original analysis that we discussed in our initial DaMoN paper. In this paper, we further broaden our analysis, detailing the effect of hardware and workload characteristics via additional real hardware platforms (IBM Power8 and 9) and the full TPC-C transaction mix. Among others, we identified clear connections between the performance of the CC schemes and hardware characteristics, especially concerning NUMA and CPU cache. Overall, we conclude that no CC scheme can efficiently make use of large multi-socket hardware in a robust manner and suggest several directions on how CC schemes and overall OLTP DBMS should evolve in future.

A reconfigurable processor for mix-precision CNNs on FPGA

To solve the problem of low computing efficiency of existing accelerators for convolutional neural network (CNNs), which caused by the inability to adapt to the characteristics of computing mode and caching for the mixed-precision quantized CNNs model, we propose a reconfigurable CNN processor in this paper, which consists of the reconfigurable adaptable computing unit, flexible on-chip cache unit and macro-instruction set. The multi-core CNN processor can be reconstructed according to the structure of CNN models and constraints of reconfigurable resources, to improve the utilization of computing resources. The elastic on-chip buffer and the data access approach by dynamically configuring an address to better utilization of on-chip memory. Then, the macroinstruction set architecture (mISA) can fully express the characteristics of the mixed-precision CNN models and reconfigurable processors, to reduce the complexity of mapping CNNs with different network structures and computing modes to reconfigurable the CNNs processors. For the well-known CNNs-VGG16 and ResNet-50, the proposed CNN processor has been implemented using Ultra96-V2 and ZCU102 FPGA, showing the throughput of 216.6 GOPS, and 214 GOPS, the computing efficiency of 0.63 GOPS/DSP and 0.64 GOPS/DSP on Ultra96-V2, respectively, achieving a better efficiency than the CNN accelerator based on fixed bit-width. Meanwhile, for ResNet-50, the throughput and the computing efficiency are up to 931.8 GOPS, 0.40 GOPS/DSP on ZCU102, respectively. In addition, these achieve up to 55.4% higher throughput than state-of-the-art CNN accelerators.

Method for increasing the degree of protection of message encryption based on an algorithm for a constant component in time

Currently, asymmetric cryptosystems are used everywhere, in document management for cryptocurrencies, providing a high level of protection to end users, relying on the mathematical complexity of calculating a discrete algorithm. But, it is possible to make a cryptocurrency attack on the so-called ephemeral key, which is an auxiliary key when creating a signature. Recent works have shown examples of cryptocurrencies on the random number generator, processor cache, timing attacks. However, these attacks do not work when the numerical value of the bits is unknown. Also, recent work shows the main vulnerability in the case signature, namely the inverse module calculation algorithm that is vulnerable to timing attacks. The article considers the damage of cryptosystems such as DSA and ECDSA before the attack based on the analysis of the variable time of signing the message. A mathematical model has been developed to test this type of lesion, based on lattice attacks. It is shown that if there are enough signatures with the same signing time, it is possible to identify the presence of common bits of ephemeral keys, which will restore the sender's private key. It is proved that the cause of the lesion is the lack of execution of the operation of calculating the inverse module of the time variable, which provides ephemeral key data to the attacker. To solve this problem, an extended Euclidean algorithm for calculating the inverse module for a fixed time is proposed. In this paper, the advanced Euclidean algorithm for calculating the inverse module is improved, namely, its constant time execution is achieved, which prevents timed attacks.

Construction of Dynamic Multiparallel Foreign Language Teaching Model Based on Multicore Processor

Heterogeneous multicore processor systems, as one of the highlights of multicore processor systems, are widely loved by people for their high efficiency and low cost, and they have also become the most commonly used processor systems in embedded systems. In the process of research on heterogeneous multicore processor systems, system task scheduling is particularly important. A good task scheduling algorithm can give full play to system performance. In this paper, the intelligent approximation algorithm is applied to the task scheduling problem of heterogeneous multicore processor system, and the heterogeneous multicore processor system is obtained as a highlight in the multicore processor system. Relying on the characteristics of high efficiency and low cost, it is widely loved by people, and at the same time, it has become the most commonly used processor system in embedded systems. In the process of research on heterogeneous multicore processor systems, the system task scheduling problem is particularly important. A good task scheduling algorithm can give full play to system performance. Some commonly used heuristic task scheduling algorithms are insufficient in solving such problems. This paper combines the granularity-based wavefront parallel decoding algorithm and the fast fusion loop filter algorithm to apply pipeline parallel technology between pixels. Decoding reconstruction module and fast loop filter module realize the fusion of multilevel parallel decoding. Based on the multicore platform, a dynamic multiparallel scheduling algorithm is designed to realize two-way video real-time parallel high-speed decoding, which improves the core resource utilization rate and decoding execution efficiency of the multicore processing platform. This paper also designs an indicator collector, a read-write hit collector, and a cache block priority determiner to implement a dynamic generation strategy with low hardware overhead. Multimodal teaching has certain feasibility and effectiveness and can have a positive impact on the English reading motivation and English reading comprehension ability of university students. Multimodal teaching improves students’ English reading comprehension ability, deepens students’ understanding and memory of words, and broadens the scope of knowledge, which has a significant promoting effect. The research results show that multimodality can be applied to college English teaching, and it can achieve better results than traditional teaching methods. By comparing the test results before and after the test, there are obvious differences between the experimental class and the control class. Whether it is the paired sample T-test of the experimental class or the independent sample T-test of two teaching methods in two classes, it proves that the scores under the multimodal English teaching mode are higher than the traditional teaching mode. Multimodal classrooms provide students with many opportunities to participate in classroom activities and form a competitive learning atmosphere. This competitive learning atmosphere has become a driving force to promote student learning. Multimodal teaching methods help to cultivate students’ independent and cooperative learning. In a multimodal classroom, many activities require cooperation and discussion among students. When they encounter difficulties, they can help each other, discuss with each other, and cooperate to complete tasks. Therefore, the multimodal teaching method will stimulate students’ interest in learning, give full play to students’ initiative, and improve students’ English ability.

High-performance reconstruction of CT medical images by using out-of-core methods in GPU

Background and objective:Since Computed Tomography (CT) is one of the most widely used medical imaging tests, it is essential to work on methods that reduce the radiation the patient is exposed to. Although there are several possible approaches to achieve this, we focus on reducing the exposure time through sparse sampling. With this approach, efficient algebraic methods are needed to be able to generate the images in real time, and since their computational cost is high, using high-performance computing is essential. Methods:In this paper we present a GPU (Graphics Processing Unit) software for solving the CT image reconstruction problem using the QR factorization performed with out-of-core (OOC) techniques. This implementation is optimized to reduce the data transfer times between disk, CPU, and GPU, as well as to overlap input/output operations and computations. Results:The experimental study shows that a block cache stored on main page-locked memory is more efficient than using a cache on GPU memory or mirroring it in both GPU and CPU memory. Compared to a CPU version, this implementation is up to 6.5 times faster, providing an improved image quality when compared to other reconstruction methods. Conclusions:The software developed is an optimized version of the QR factorization for GPU that allows the algebraic reconstruction of CT images with high quality and resolution, with a performance that can be compared with state-of-the-art methods used in clinical practice. This approach allows reducing the exposure time of the patient and thus the radiation dose.

Noise-Free Security Assessment of Eviction Set Construction Algorithms with Randomized Caches

Cache timing attacks, i.e., a class of remote side-channel attack, have become very popular in recent years. Eviction set construction is a common step for many such attacks, and algorithms for building them are evolving rapidly. On the other hand, countermeasures are also being actively researched and developed. However, most countermeasures have been designed to secure last-level caches and few of them actually protect the entire memory hierarchy. Cache randomization is a well-known mitigation technique against cache attacks that has a low-performance overhead. In this study, we attempted to determine whether address randomization on first-level caches is worth considering from a security perspective. In this paper, we present the implementation of a noise-free cache simulation framework that enables the analysis of the behavior of eviction set construction algorithms. We show that randomization at the first level of caches (L1) brings about improvements in security but is not sufficient to mitigate all known algorithms, such as the recently developed Prime–Prune–Probe technique. Nevertheless, we show that L1 randomization can be combined with a lightweight random eviction technique in higher-level caches to mitigate known conflict-based cache attacks.

Understanding I/O Direct Cache Access Performance for End Host Networking

Direct Cache Access (DCA) enables a network interface card (NIC) to load and store data directly on the processor cache, as conventional Direct Memory Access (DMA) is no longer suitable as the bridge between NIC and CPU in the era of 100 Gigabit Ethernet. As numerous I/O devices and cores compete for scarce cache resources, making the most of DCA for networking applications with varied objectives and constraints is a challenge, especially given the increasing complexity of modern cache hardware and I/O stacks. In this paper, we reverse engineer details of one commercial implementation of DCA, Intel's Data Direct I/O (DDIO), to explicate the importance of hardware-level investigation into DCA. Based on the learned knowledge of DCA and network I/O stacks, we (1) develop an analytical framework to predict the effectiveness of DCA (i.e., its hit rate) under certain hardware specifications, system configurations, and application properties; (2) measure penalties of the ineffective use of DCA (i.e., its miss penalty) to characterize its benefits; and (3) show that our reverse engineering, measurement, and model contribute to a deeper understanding of DCA, which in turn helps diagnose, optimize, and design end-host networking.

Enabling efficient sub-block disabled caches using coarse grain spatial predictions

Reducing the supply voltage in today′s process technologies introduces significant reliability challenges for on-chip SRAM arrays. As a reaction, many Cache Fault-Tolerance (CFT) techniques have been developed to ensure error free and performance efficient execution in the presence of faults. A class of recent CFT techniques are based on the concept of disabling cache portions, such as (sub-)blocks or words that include defective bits, and reconfiguring operational ones (e.g., physical or logical neighbor (sub-)blocks). All those techniques require significant circuit modifications which may pose unacceptable overheads to time-sensitive L1 caches. In this work we propose to deal with the cache reliability problem at a very different level. We assume that faulty caches are enhanced with the ability of disabling their defective parts at different sub-block granularities. The key idea is to leverage the spatial reuse patterns of the memory blocks (not all the data fetched into the cache is accessed) in order to mask out the additional, due-to-faults, cache misses. To this end, we propose a new class of frugal spatial predictors (with 24-bytes storage requirements) to orchestrate the replacement decisions of the fully and partially functional cache blocks. Our evaluation results reveal that the proposed approach is able to offer 32.3% on average, among all studied percentage of failures, increase in hit ratio in first level data caches (64.6% in instruction caches) over a conventional faulty cache (based on block disabling). Further, experimental results reveal the superiority of the proposed method with respect to Instructions-Per-Cycle and Energy-Delay-Product.

Deep-Sea: A Reconfigurable Accelerator for Classic CNN

To meet the changing real-time edge engineering application requirements of CNN, aiming at the lack of universality and flexibility of CNN hardware acceleration architecture based on ARM+FPGA, a general low-power all pipelined CNN hardware acceleration architecture is proposed to cope with the continuously updated CNN algorithm and accelerate in hardware platforms with different resource constraints. In the framework of the general hardware architecture, a basic instruction set belonging to the architecture is proposed, which can be used to calculate and configure different versions of CNN algorithms. Based on the instruction set, the configurable computing subsystem, memory management subsystem, on-chip cache subsystem, and instruction execution subsystem are designed and implemented. In addition, in the processing of convolution results, the on-chip storage unit is used to preprocess the convolution results, to speed up the activation and pooling calculation process in parallel. Finally, the accelerator is modeled at the RTL level and deployed on the XC7Z100 heterogeneous device. The lightweight networks YOLOv2-tiny and YOLOv3-tiny commonly used in engineering applications are verified on the accelerator. The results show that the peak performance of the accelerator reaches 198.37 GOP/s, the clock frequency reaches 210 MHz, and the power consumption is 4.52 w under 16-bit width.

NBTree

Persistent memory (PM) promises near-DRAM performance as well as data persistency. Recently, a new feature called eADR is available on the 2 nd generation Intel Optane PM with the 3 rd generation Intel Xeon Scalable Processors. eADR ensures that data stored within the CPU caches will be flushed to PM upon the power failure. Thus, in eADR-enabled PM systems, the globally visible data is considered persistent, and explicit data flushes are no longer necessary. The emergence of eADR presents unique opportunities to build lock-free data structures and unleash the full potential of PM. In this paper, we propose NBTree, a lock-free PM-friendly B + -Tree, to deliver high scalability and low PM overhead. To our knowledge, NBTree is the first persistent index designed for eADR-enabled PM systems. To achieve lock-free, NBTree uses atomic primitives to serialize leaf node operations. Moreover, NBTree proposes four novel techniques to enable lock-free access to the leaf during structural modification operations (SMO), including three-phase SMO, sync-on-write, sync-on-read , and cooperative SMO. For inner node operations, we develop a shift-aware search algorithm to resolve read-write conflicts. To reduce PM overhead, NBTree decouples the leaf nodes into a metadata layer and a key-value layer. The metadata layer is stored in DRAM, along with the inner nodes, to reduce PM accesses. NBTree also adopts log-structured insert and in-place update/delete to improve cache utilization. Our evaluation shows that NBTree achieves up to 11X higher throughput and 43X lower 99% tail latency than state-of-the-art persistent B + -Trees under YCSB workloads.

HeapCheck: Low-cost Hardware Support for Memory Safety

Programs written in C/C++ are vulnerable to memory-safety errors like buffer-overflows and use-after-free. While several mechanisms to detect such errors have been previously proposed, they suffer from a variety of drawbacks, including poor performance, imprecise or probabilistic detection of errors, or requiring invasive changes to the ISA, binary-layout, or source-code that results in compatibility issues. As a result, memory-safety errors continue to be hard to detect and a principal cause of security problems. In this work, we present a minimally invasive and low-cost hardware-based memory-safety checking framework for detecting out-of-bounds accesses and use-after-free errors. The key idea of our mechanism is to re-purpose some of the “unused bits” in a pointer in 64-bit architectures to store an index into a bounds information table that can be used to catch out-bounds errors and use-after-free errors without any change to the binary layout. Using this memory-safety checking framework, we enable HeapCheck, a design for detecting Out-of-bounds and Use-after-free accesses for heap-objects, that are responsible for the majority of memory-safety errors in the wild. Our evaluations using C/C++ SPEC CPU 2017 workloads on Gem5 show that our solution incurs 1.5% slowdown on average, using an 8 KB on-chip SRAM cache for caching bounds-information. Our mechanism allows detection of out-of-bounds errors in user-code as well as in unmodified shared-library functions. Our mechanism has detected out-of-bounds accesses in 87 lines of code in the SPEC CPU 2017 benchmarks, primarily in Glibc v2.27 functions, that, to our knowledge, have not been previously detected even with popular tools like Address Sanitizer.

Effectiveness Evaluation of Replacement Policies for On-Chip Caches in Multiprocessors

A Cache plays a vital role in improving performance in the multicore environment, especially the Last Level Cache (LLC). The improvements in performance are based on the block size, associativity, and replacement policies. Most of the papers concentrate on traditional Least Recently Used (LRU) based replacement policies for their replacement decisions. Unfortunately, the replacement decisions do not enhance performance of the cache as expected. An enhanced modified Pseudo LRU policy is proposed, which is an approximation of LRU. The proposed methodology uses counters to enhance the confidence of replacement decisions based on the history of the replaceable blocks in cache. It is very clear from the Simulation results that the replacement scheme proposed exhibits better performance improvement in terms of miss ratio of about 3% and energy efficiency of about 2% on an average.

Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

SSD internal cache management policies: A survey

SSDs are now increasingly being adopted as primary nonvolatile storage in diverse domains. The internal caches in the SSDs boost SSD performance, lifetime, and robustness. There are three types of internal caches: data cache and mapping cache in the SSD front-end, and flash-based cache in the SSD back-end; they are designed to meet specific requirements like controlling traffic to the back-end, optimization of response time, improving SSD lifetime etc. The underlying memory technology also influences cache design decisions. This work aims to present a methodological survey of cache management policies for these three types of internal caches in SSD. In particular, our work (a) makes a taxonomical classification of cache management policies for each of the cache types and performs a comparative analysis of the research works in each micro-category, (b) derives a set of guidelines that can be helpful for a future cache designer, and (c) enumerates a number of future research directions for designing an optimal SSD internal cache management policy. Our work is distinct from other studies in that we analyze policies for all three types of SSD internal caches, whereas this has not been done in the prior surveys.

Tightening the CRPD bound for multilevel non-inclusive caches

Tasks running on microprocessors with cache memories are often subjected to cache related preemption delays (CRPDs). CRPDs may significantly increase task execution times, thereby, affecting their schedulability. Schedulability analysis accounting for the impact of CRPD has been extensively studied over the past two decades for systems with a single level of cache. Yet, the literature on CRPD for multilevel non-inclusive caches is relatively scarce . Two main challenges exist when analyzing multilevel caches: (1) characterization of the indirect effect of preemption , i.e., capturing the increase in cache interference at lower cache levels (e.g., level-two or L2 cache) due to the evictions of cache content from a higher cache level (e.g., level-one or L1 cache), and (2) upper bounding the maximum CRPD suffered by tasks at lower cache levels (e.g., L2 cache), i.e., determining the cache content of tasks that can be evicted from lower cache levels in case of preemptions. Existing analysis that focus on bounding CRPD for multilevel non-inclusive caches overestimate the values of (1) and (2) leading to pessimistic worst-case response time (WCRT) estimations. In this work, we reduce the excessive pessimism of the state-of-the-art CRPD analysis for multilevel non-inclusive caches by (i) introducing the notion of multi-level useful cache blocks, i.e., cache blocks that can cause CRPD at different cache levels, and use it to compute a tighter bound on the indirect effect of preemption of tasks; and (ii) deriving a new analysis to compute tighter bounds on the CRPD of tasks at lower cache levels (e.g., L2 cache). We performed a thorough experimental evaluation using benchmarks to compare the performance of our proposed CRPD analysis against the state-of-the-art CRPD analysis. Experimental results show that our proposed CRPD analysis dominates the existing analysis and improves task set schedulability by up to 20% percentage points.

Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation

As the memory footprint of emerging applications keeps increasing, the address translation becomes a critical performance bottleneck due to frequent misses on TLB. In addition, the TLB miss penalty becomes more critical in modern computer systems because the levels of the hierarchical page table (a.k.a. radix page table) are increasing to extend address space. In order to reduce the TLB misses, modern high-performance processors employ a multi-level TLB structure that uses a large last-level TLB. Employing a large last-level TLB might reduce the TLB misses. However, its capacity is still limited, and it can incur chip area overheads. In this paper, we propose a PSE Pinning mechanism that provides a large PSE (Page Structure Entry) store by dedicating some space of the last-level cache for only storing the page structure entries. PSE Pinning is based on three key observations. First, memory-intensive applications suffer from frequent misses on the last-level cache. Thus, most space of the last-level cache is not well utilized. Second, most PSEs are fetched from the main memory during the page table walk process, meaning the cache lines for the PSEs are frequently evicted from the on-chip caches. Lastly, a small number of PSEs are frequently accessed while others are not. By exploiting these three observations, PSE Pinning pins the frequently accessed page structure entries to the last-level caches so that they can reside on the cache. Experimental results show that PSE Pinning improves the performance of memory-intensive workloads suffering from frequent L2 TLB misses by 7.8% on average.

Optimizing the Performance of Data Warehouse by Query Cache Mechanism

Fast access of data from Data Warehouse (DW) is a need for today’s Business Intelligence (BI). In the era of Big Data, the cache is regarded as one of the most effective techniques to improve the performance of accessing data. DW has been widely used by several organizations to manage data and use it for Decision Support System (DSS). Many methods have been used to optimize the performance of fetching data from DW. Query cache method is one of those methods that play an effective role in optimization. The proposed work is based on a cache-based mechanism that helps DW in two aspects: the first one is to reduce the execution time by directly accessing records from cache memory, and the second is to save cache memory space by eliminating non-frequent data. Our target is to fill the cache memory with the most used data. To achieve this goal aging-based Least Frequently Used (LFU) algorithm is used by considering the size and frequency of data simultaneously. The priority and expiry age of the data in the cache memory is managed by dealing with both the size and frequency of data. LFU sets priorities and counts the age of data placed in cache memory. The entry with the lowest age count and priority is eliminated first from the cache block. Ultimately, the proposed cache mechanism efficiently utilized cache memory and fills a large performance gap between the main DW and the business user query.

Cache Memory Design for Single Bit Architecture with Different Sense燗mplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power. Unfortunately, however, STT-MRAM suffers from its long write latency and high write energy consumption. This paper proposes a cache management technique called Proactive Invalidation (PROI) that proactively invalidates dead blocks in advance to enable fast writes in the STT-MRAM caches. Experimental evaluation shows that the proposed technique improves performance by 14% on average compared to the baseline STT-MRAM cache. This paper also proposes two optimization techniques called Proactive Invalidation-aware Data Encoding (PIDE) and Narrowness-aware Partial Write (NPW) to minimize the energy overheads of Proactive Invalidation. Experimental results demonstrate that the total energy consumption of the STT-MRAM cache with PROI is only 1.8% higher than the baseline when PROI is applied with PIDE and NPW.