Total Wire Length Research Articles

Segmented All-Platinum Nanowires with Controlled Morphology through Manipulation of the Local Electrolyte Distribution in Fluidic Nanochannels during Electrodeposition

Synthesis of segmented all-Pt nanowires is achieved by a template-assisted method. The combination of a suitably chosen electrolyte/template system with pulse-reverse electrodeposition allows the formation of well-defined segments linked to nanowires. Manipulation of the morphology is obtained by controlling the electrokinetic effects on the local electrolyte distribution inside the nanochannels during the nanowire growth process, allowing a deviation from the continuously cylindrical geometry given by the nanoporous template. The length of the segments can be adjusted as a function of the cathodic pulse duration. Applying constant pulses leads to segments with homogeneous shape and dimensions along most of the total wire length. X-ray diffraction demonstrates that the preferred crystallite orientation of the polycrystalline wires varies with the average segment length. The results are explained considering transitions in texture formation with increasing thickness of the electrodeposit. A mechanism of segment formation is proposed based on structural characterizations. Nanowires with controlled segmented morphology are of great technological importance, because of the possibility to precisely control their substructure as a means of tuning their electrical, thermal, and optical properties. The concept we present in this work for electrodeposited platinum and track-etched polycarbonate membranes can be applied to other selected materials as well as templates and constitutes a general method to controlled nanostructuring and synthesis of shape controlled nanostructures.

3-D System-on-System (SoS) Biomedical-Imaging Architecture for Health-Care Applications

This paper presents the implementation of a 3-D architecture for a biomedical-imaging system based on a multilayered system-on-system structure. The architecture consists of a complementary metal-oxide semiconductor image sensor layer, memory, 3-D discrete wavelet transform (3D-DWT), 3-D Advanced Encryption Standard (3D-AES), and an RF transmitter as an add-on layer. Multilayer silicon (Si) stacking permits fabrication and optimization of individual layers by different processing technology to achieve optimal performance. Utilization of through silicon via scheme can address required low-power operation as well as high-speed performance. Potential benefits of 3-D vertical integration include an improved form factor as well as a reduction in the total wiring length, multifunctionality, power efficiency, and flexible heterogeneous integration. The proposed imaging architecture was simulated by using Cadence Spectre and Synopsys HSPICE while implementation was carried out by Cadence Virtuoso and Mentor Graphic Calibre.

Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews

The area-input/output (I/O) flip-chip package provides a high chip-density solution to the demand of more I/Os in very large scale integration designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple re-distribution layer (RDL) routing problem (without RDL vias) for flip-chip designs, considering pin and layer assignment, signal integrity, signal-skew and total wirelength minimization, and chip-package co-design. Our router adopts a two-stage technique of global routing followed by RDL routing. The global routing assigns each block port to a unique bump pad via an I/O pad and decides the RDL routing among I/O pads and bump pads. Based on the minimum-cost maximum-flow algorithm, we can guarantee 100% RDL routing completion after the assignment and the optimal solution with the minimum wirelength. The RDL routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. Experimental results based on 12 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable central processing unit times, while related works cannot.

Skew compensation in energy recovery clock distribution networks

In this study a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: fast , standard and slow are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the clock port of the flip-flops. A fast/slow flip-flop has a shorter/longer T DQ delay, compared with a standard flip-flop for the same setup time (T DCLK ). Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal clock signal used in energy recovery clock distribution networks compared to the conventional square-wave clock, the skew that can be compensated for in energy recovery clock distribution networks using this approach would be much higher than in square-wave clock distribution networks. This approach increases the skew bounds required by algorithms to balance the skew in the clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% 1of the clock period can be compensated for in the example used. In addition, constructing clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the clock tree using buffers was not considered here since inserting a buffer in the clock's path eliminates the energy recovery property. As an example of illustrating the proposed methodology, the authors have used the Elmore delay model with a selected energy recovery flip-flop to verify the practicality of the proposed scheme. Better results can be obtained by using different flip-flops. The method can generally be applied to energy recovery or square-wave clocking if different flip-flops of various speeds are used.

A Degree-Based Clustering Technique for VLSI Placement

In this paper, clustering for the circuit placement problem is examined from the perspective of wire length contribution from groups of nets. First, the final wire length data of groups of nets with different degrees are extracted and studied. It is illustrated that nets with high-degree contribute a high percentage to the total wire length. To remedy this problem, a clustering algorithm for placement is proposed that focuses on clustering nets with high-degree. This new clustering algorithm is implemented as a preprocessing step in the placement stage. ICCAD04 benchmark circuits abstracted from IBM are used to validate the placement quality by using four academic placers with and without the proposed preprocessing step. Experiments show that the overall placement results can be improved by up to 5%.

Discrete cooperative particle swarm optimization for FPGA placement

Particle swarm optimization (PSO) is a stochastic optimization technique that has been inspired by the movement of birds. On the other hand, the placement problem in field programmable gate arrays (FPGAs) is crucial to achieve the best performance. Simulated annealing algorithms have been widely used to solve the FPGA placement problem. In this paper, a discrete PSO (DPSO) version is applied to the FPGA placement problem to find the optimum logic blocks and IO pins locations in order to minimize the total wire-length. Moreover, a co-operative version of the DPSO (DCPSO) is also proposed for the FPGA placement problem. The problem is entirely solved in the discrete search space and the proposed implementation is applied to several well-known FPGA benchmarks with different dimensionalities. The results are compared to those obtained by the academic versatile place and route (VPR) placement tool, which is based on simulated annealing. Results show that both the DPSO and DCPSO outperform the VPR tool for small and medium-sized problems, with DCPSO having a slight edge over the DPSO technique. For higher-dimensionality problems, the algorithms proposed provide very close results to those achieved by VPR.

A single layer zero skew clock routing in X architecture

With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our Planar-CRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.

WireMap

This article presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the iterative mapping optimization to reduce the total number of pin-to-pin connections (or edges). On academic benchmark (ISCAS, MCNC, and ITC designs), the average edge reduction of 9.3% is achieved while maintaining depth and LUT count compared to state-of-the-art technology mapping. Placing and routing the resulting netlists leads to an 8.5% reduction in the total wirelength, a 6.0% reduction in minimum channel width, and a 2.3% reduction in critical path delay. This technique is applied in the Xilinx ISE Design tool to evaluate its effect on industrial Virtex5 circuits. In a set of 20 large designs, we find the edge reduction is 6.8% while total wirelength measured in the placer is reduced by 3.6%. Applying WireMap has an additional advantage of reducing an average number of inputs of LUTs without increasing the total LUT count and depth. The percentages of 5- and 6-LUTs in a typical design are reduced, while the percentages of 2-, 3-, and 4-LUTs are increased. These smaller LUTs can be merged into pairs and implemented using the dual-output LUT structure found in commercial FPGAs. For academic benchmarks, WireMap leads to 9.4% fewer dual-output LUTs after merging. For the industrial designs, WireMap leads to 6.3% fewer dual-output Virtex5 LUTs.

Optimal design of HTS magnets for a modular toroid-type 2.5 MJ SMES using multi-grouped particle swarm optimization

Superconducting magnetic energy storage (SMES) is one of the promising power system applications of superconducting technology and has been actively researched and developed worldwide. Generally, there are three types of SMES-solenoid, multiple solenoid, and toroid. Among these types, toroid type seems to require more wires than solenoid type and multiple solenoid type at the same operating current. However toroid type reduces normal field in the wire and stray field dramatically because magnetic field is confined inside the coil. So, the total length of wire in the toroid type can be reduced in comparison with that in the solenoid type by increasing operating current. In this paper, a 2.5 MJ class SMES with HTS magnets of single solenoid, multiple solenoid and modular toroid type were optimized using a recently developed multi-modal optimization technique named multi-grouped particle swarm optimization (MGPSO). The objective of the optimization was to minimize the total length of HTS superconductor wires satisfying some equality and inequality constraints. The stored energy and constraints were calculated using 3D magnetic field analysis techniques and an automatic tetrahedral mesh generator. Optimized results were verified by 3D finite element method (FEM).

Efficient Hierarchical Algorithm for Mixed Mode Placement in Three Dimensional Integrated Circuit Chip Designs

Hierarchical art was used to solve the mixed mode placement for three dimensional (3-D) integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional (2-D) global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.

Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements

Zigzag power gating (ZPG) can overcome the long wake-up delay of standard power gating, but its requirement for both nMOS and pMOS current switches, in a zigzag pattern, requires complicated power networks, limiting application to custom designs. We propose a design framework for cell-based semicustom design of ZPG circuits, using a new power network architecture that allows the unmodified conventional logic cells to be combined with custom circuitry such as ZPG flip-flops, input forcing circuits, and current switches. The design flow, from register transfer level description to layout, is described and applied to a 32-b microprocessor design using a 1.2-V 65-nm triple-well bulk CMOS process. The use of a sleep vector in ZPG requires additional switching power when entering standby mode and returning to active mode. The switching power should be minimized so that is does not outweigh the leakage saved by employing ZPG scheme. We formulate the selection of a sleep vector as a multiobjective optimization problem, minimizing both the transition energy and the total wirelength of a design. We solve the problem by employing multiobjective genetic-based algorithm. Experimental results show an average saving of 39% in transition energy and 8% in total wirelength for several benchmark circuits in 65-nm technology.

In Mammalian Muscle, Axonal Wiring Takes Surprising Paths

From at least the dawn of the electronic age, the oddballs among us have been described as being “wired differently.” If that's so, then a new study suggests we are probably all oddballs. By mapping the paths and branch points of individual axons reaching out to a single muscle, Ju Lu, Jeff Lichtman, and colleagues show that even for one of the smallest muscles in a mouse, the wiring diagram differs between two individuals, and even between the left and right sides of the same mouse. A complete wiring diagram—where axons go, how they branch, and where they link to muscle—has been developed for roundworms, but never before for a mammal. Performing the same feat in the mouse has presented an enormous technical challenge because of the larger size and complexity of the nervous system. The authors chose to study the interscutularis muscle, which connects the base of the ear to the middle of the skull, because it was small, accessible, and innervated by relatively few neurons. Using mice whose cells all bore a fluorescent tag, and a confocal microscope with a computer-controlled, motorized stage, the authors took thousands of individual photographs and reconstructed them to trace individual axons as they stretched across the skull, entered the muscle, branched repeatedly, and ultimately formed synapses with individual muscle fibers. Even with computers humming at full speed, tracing a single axon along its 7-millimeter average length took about 14 hours, and each muscle contained roughly 14 axons. The mouse interscutularis muscle connectome. The complete set of innervating motor axons, imaged with confocal microscopy, gives the anatomical underpinning of the graded tensions elicited by motor neurons according to Henneman's size principle. (Image ... But averages hide the details and the differences among individual muscles that were the very point of the study. In the worm, the routes taken and connections made by axons are highly stereotyped, indicating a high degree of genetic control. But in the mouse, the actual number of axons innervating a single muscle ranged from 13 to 16, differing between mice and even between the left and right sides of the same mouse. Axonal length, including all the branches, varied much more widely, from 1.5 millimeters to 13.3 millimeters, and the number of synapses formed by a single axon ranged from a low of one (for an axon that didn't branch at all) to a high of 37. The branching pattern of axons that innervate a similar number of muscle fibers from different muscles also differed significantly, suggesting that unlike in the worm, branching in the mammal is not a deterministic process; instead it is governed by some general developmental rules, while the details of final connection are shaped by contingencies, as excess synapses are pruned. A single axon, together with the muscle fibers it stimulates, is called a motor unit, and previous measurements of the force generated by fiber contraction (“twitch tension”) have revealed that there is a characteristic range of such twitch tensions in each muscle. In their study, the authors showed that the distribution of motor unit sizes they identified correlates with the range of twitch tensions, providing an anatomical basis for what had previously been only a physiological observation. A long-held principle, dating back to the famed neuroanatomist Cajal, dictates that the total wiring length in a branched axon should be minimized, since the energy costs for conduction increase with length. Not so in the mouse, the authors found, where almost every axon was longer than optimal, and could have been shortened had the branches occurred elsewhere or the axon followed a different available nerve path through the muscle. They calculated the extraneous length at 25% of the total. However, they note, there may be little substantive penalty for this extra tissue, since the energy cost of muscle contraction is far higher than that of axonal conduction. This study is only the beginning of mapping “connectomes” for mammalian neural circuits. While the general principles seen in the interscutularis muscle may apply elsewhere, there is every reason to suspect that the details will differ. The connectome of even a single other muscle will offer further insight into the balance of chance and necessity in muscle wiring. In principle, similar techniques could be used to tease out connection patterns in the brain, although that challenge would dwarf the Herculean efforts required in this study.

Speeding Up FPGA Placement via Partitioning and Multithreading

One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing‐based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region‐based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of 2.5× using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation

In 3D IC design, thermal issue is a critical challenge. To eliminate hotspots, physical layouts are always adjusted by some incremental changes, such as shifting or duplicating hot blocks. In this paper, we distinguish the thermal-aware incremental changes in three different categories: migrating computation, growing unit and moving hotspot blocks. However, these modifications may degrade the packing area as well as interconnect distribution greatly. In this paper, mixed integer linear programming (MILP) models are devised according to these different incremental changes so that multiple objectives can be optimized simultaneously. Furthermore, to avoid random incremental modification, which may be inefficient and need long runtime to converge, here potential gain is modeled for each candidate incremental change. Based on the potential gain, a novel thermal optimization flow to intelligently choose the best incremental operation is presented. Experimental results show that migrating computation, growing unit and moving hotspot can reduce max on-chip temperature by 7%, 13% and 15% respectively on MCNC/GSRC benchmarks. Still, experimental results also show that the thermal optimization flow can reduce max on-chip temperature by 14% to the initial packings generated by an existing 3D floorplanning tool CBA, and achieve better area and total wirelength improvement than individual operations do. The results with the initial packings from CBA_T (Thermal-aware CBA floorplanner) show that 13.5% temperature reduction can be obtained by our incremental optimization flow.

Congestion-Driven Multilevel Full-Chip Routing Framework

A W-shaped multilevel full-chip routing framework using W-shaped optimization flow is used to find the final routing solution. The W-shaped flow consists of two sequential V-shaped optimization flows. The first V-shaped flow optimizes the global routing solution. The probabilistic congestion prediction technique is used to guide the global routing decision to find the routing solution that evenly distributes the nets. Then, the second V-shaped flow improves the quality of the routing result. Tests on a set of commonly used benchmark circuits and comparisons with other multilevel routing systems show that the routability, total wire length, total number of vias, and the runtime are all improved.

Block flipping and white space distribution for wirelength minimization

Floorplanning plays an important role in the physical design of very large scale integration (VLSI) circuits. Traditional floorplanners use heuristics to optimize a floorplan based on multiple objectives. Besides traditional floorplanning approaches, some post-floorplanning steps can be applied to consider block flipping, pin assignment and white space distribution to optimize the performance. If we can consider the above three optimizations simultaneously as a post-floorplanning step, the total wirelength can be further reduced without modifying the original floorplan topology. Experimental results show that our approach can handle these issues simultaneously and wirelength can be further improved with a small penalty in runtime. Thus, this approach is highly desirable to be incorporated into a floorplanner as a post-processing step for wirelength optimization.

A FAST AND EFFECTIVE TIMING-DRIVEN PLACEMENT TOOL FOR FPGAs

In this paper, we present TQPF, a Timing-Driven Quadratic-based Placement Tool for FPGAs. Quadratic placement algorithms try to minimize total squared wire length by solving linear equations. The resulting placement tends to locate all cells near the center of the chip with a large amount of overlap. Also, since squared wire length is only an indirect measure of linear wire length, the resulting total wire length may not be minimized. We propose methods to alleviate the above two problems that give high-quality results while minimizing the total run time. We incorporate multiple iterations of equation-solving process together with a technique for pulling nodes out of the dense area while minimizing linear wire length. Experimental results using 20 Microelectronics Center of North Carolina (MCNC) benchmark circuits show that, on average, TQPF is approximately three times faster than the well-known Versatile Placement and Routing tool for FPGAs (VPR). The estimated total wire length, on average, is only 1.4% longer, and the critical path delay is 4.9% lower.

High-Performance Routing at the Nanometer Scale

In this paper, we describe significant improvements to core routing technologies and outperform the best results from the International Symposium on Physical Design 2007 Global Routing Contest and the International Conference on Computer-Aided Design 2007 in terms of route completion and total wirelength.

Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction

It is well known that the problem of constructing a timing-driven rectilinear Steiner tree for any signal net is important in performance-driven designs and has been extensively studied. Until now, many efficient approaches have been proposed for the construction of a timing-driven rectilinear Steiner tree. As technology process advances, +45° and −45° diagonal segments can be permitted in an octilinear routing model. To our knowledge, no approach is proposed to construct a timing-driven octilinear Steiner tree for any signal net. In this paper, given a rectilinear Steiner tree for any signal net, we propose an efficient transformation-based approach to construct a timing-driven octilinear Steiner tree based on the computation of the octilinear distance and the concept of Steiner-point reassignment and path reconstruction in an octilinear routing model. The experimental results show that our proposed transformation-based approach can use reasonable CPU time to construct a TOST, and a 10%--18% improvement in timing delay and a 5%--14% improvement in total wire length in the original RSTs are obtained in the construction of TOSTs for the tested signal nets.

Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs

Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph, this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any two-pin net and many higher pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works.