Block flipping and white space distribution for wirelength minimization

Abstract

Floorplanning plays an important role in the physical design of very large scale integration (VLSI) circuits. Traditional floorplanners use heuristics to optimize a floorplan based on multiple objectives. Besides traditional floorplanning approaches, some post-floorplanning steps can be applied to consider block flipping, pin assignment and white space distribution to optimize the performance. If we can consider the above three optimizations simultaneously as a post-floorplanning step, the total wirelength can be further reduced without modifying the original floorplan topology. Experimental results show that our approach can handle these issues simultaneously and wirelength can be further improved with a small penalty in runtime. Thus, this approach is highly desirable to be incorporated into a floorplanner as a post-processing step for wirelength optimization.