PEEC capacitance extraction of 3-D interconnects

Abstract

As feature size of electronic devices decreases, fast and accurate capacitance extraction has become increasingly critical for verification and analysis as regard as electromagnetic compat- ibility and signal integrity issues. The partial element equivalent circuit method is implemented for three-dimensional capacitance extraction of interconnects and very large-scale integration circuits with multiple dielectrics. The electric field coupling due to free and bound charges are analysed and modelled separately thus allowing to distinguish their contribution. The proposed approach provides physical insight, totally compatible fast methods for accelerating matrix-vector products, allows an easy treatment of lossy and dispersive dielectrics and is well suited for applying model order reduction techniques. Modern electronic design is surely extremely challenging. It is known that power distribution and management, digital computing and radio frequency wireless communication have very different bandwidths, as well as voltage and current levels. In addition, today's mobile devices share the same printed circuit board and/or packaging substrate in a very dense design. The consequence of this fact is that parasitics and interference poses significant design challenges and deserves a special attention to electromag- netic compatibility (EMC) engineers to meet design requirements. Parasitics may compromise the signal fidelity and/or level and dominate the coupling in the case of elec- tromagnetic interference and immunity. Typically, coupling takes place through the electric field (capacitive coupling), magnetic field (inductive coupling) or through a common current return path. It is understood that design meeting EMC criteria has a critical need for methodologies and computer-aided design tools, which allow to predict para- sitic effects and capture coupling physics. Also it is extre- mely desirable to extract parasitic lumped element circuit models from a layout geometry. As the feature size of electronics in mobile devices has dramatically decreased, the interconnect is becoming a dominant factor in system delay and signal integrity (SI). An accurate and efficient electromagnetic modelling of three-dimensional (3-D) high speed interconnects and very large-scale integration (VLSI) circuits embedded in mul- tiple dielectrics is extremely important for the design and verification of nowadays systems on package and systems on-chip for communication systems. Circuit performances such as SI, EMC, delay, radiation, power consumption, reliability are strongly influenced by the electrical charac- teristics of interconnects. Among the other effects, timing verification requires accurate interconnect modelling of parasitic parameters especially as regard as the parasitic