Total Wire Length Research Articles

Single-layer obstacle-aware routing for substrate interconnections

Due to the limit of available layers and the existence of obstacles in a routing region, single-layer obstacle-aware routing becomes an important issue for substrate interconnections. In this paper, based on the terminals of the given nets, the corner of the rectangular obstacles and the routing plane, routability-driven constrained Delaunay triangulation can be firstly constructed. Furthermore, based on the construction of routability-driven constrained Delaunay triangles, a flow-based approach is proposed to assign the global wires of the given nets in a single layer and an efficient approach is proposed to assign the physical paths of the given nets for single-layer obstacle-aware routing. Compared with the 97.35% routability of the routing nets in the modified combination of Liu׳s topological router [13] and our proposed detailed router for substrate routing with the rectangular obstacles, the experimental results show that our proposed flow-based approach can use less CPU time to obtain the 99.90% routability of the routing nets and shorter total wirelength in a single layer on the average for the tested examples.

Nonsmooth Optimization Method for VLSI Global Placement

The common objective of very large-scale integration (VLSI) placement problem is to minimize the total wirelength, which is calculated by the total half-perimeter wirelength (HPWL). Since the HPWL is not differentiable, various differentiable wirelength approximation functions have been proposed in analytical placement methods. In this paper, we reformulate the HPWL as an l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -norm model of the wirelength function, which is exact but nonsmooth. Based on the l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -norm wirelength model and exact calculation of overlapping areas between cells and bins, a nonsmooth optimization model is proposed for the VLSI global placement problem, and a subgradient method is proposed for solving the nonsmooth optimization problem. Moreover, local convergence of the subgradient method is proved under some suitable conditions. In addition, two enhanced techniques, i.e., an adaptive parameter to control the step size and a cautious strategy for increasing the penalty parameter, are also used in the nonsmooth optimization method. In order to make the placement method scalable, a multilevel framework is adopted. In the clustering stage, the best choice clustering algorithm is modified according to the l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -norm wirelength model to cluster the cells, and the nonsmooth optimization method is recursively used in the declustering stage. Comparisons of experimental results on the International Symposium on Physical Design (ISPD) 2005 and 2006 benchmarks show that the global placement method is promising.

TSV Replacement and Shield Insertion for TSV–TSV Coupling Reduction in 3-D Global Placement

Through silicon via (TSV) cross coupling can seriously degrade circuit performance of 3-D ICs if it is not considered during design. In this paper, we propose two algorithms which combine coupling-aware TSV placement with shield insertion to yield better results than either technique alone. We first introduce an algorithm for TSV placement assuming a fixed standard cell placement. The result of this algorithm is a 13% reduction in worst case coupling across all TSV pairs and a 90% reduction in the total number of TSV pairs violating an imposed coupling threshold. We then introduce a second algorithm that perturbs a given standard cell and TSV placement to improve coupling. This second algorithm yields a 17% reduction in worst case coupling and removes all coupling violations. Both algorithms cause wirelength (WL) to increase no more than 5%. Our algorithms offer a large improvement to TSV-TSV coupling at the expense of only a meager degradation of total WL, and in many designs and applications this trade-off is well justified.

Designs of 10 MW Air-core and Iron-core HTS Wind Power Generators

High Temperature Superconducting (HTS) synchronous generators can be designed with either an air-core type or iron-core type. The air-core type has higher efficiency under rated rotating speed and load than the iron-core type because of the iron losses which may produce much heat. However, the total length of HTS wire in the air-core type is longer than the iron-core type because the generated magnetic flux density of the air-core type is low. This paper deals with designs of 10 MW air-core and iron-core HTS wind power generators for wind turbines. Fully air-core, partially iron-core, and fully iron-core HTS generators are designed, and various stator winding methods in the three HTS generators are also considered, such as short-pitch concentrated winding, full-pitch concentrated winding, short-pitch distributed winding, and full-pitch distributed winding. These HTS generators are analyzed using a 3D finite elements method program. The analysis results of the HTS generators are discussed in detail, and the results will be effectively utilized for large-scale wind power generation systems.

Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage

Three-dimensional integration technology is proposed to break down long wires and increase integration level of emerging complex designs. However, efficiency of this technology heavily depends on the usage of Through-Silicon Vias. TSVs are key solutions for cooling the 3D-chips but they occupy considerable silicon area. Therefore, reducing the number of required TSVs in routing step is very critical in 3D-chips. In this paper, a TSV multiplexing approach is proposed to reduce the number of required routing TSV. We proposed two multiplexed 3D-switchbox architectures. In the first architecture, the TSVs inside the switchboxes are multiplexed while in the second architecture, TSVs are multiplexed between the switchboxes. Moreover, a routing algorithm is suggested to route the FPGA using the multiplexed switchboxes to evaluate the proposed architectures. Experimental results show that the presented architectures and algorithms reduce the number of used TSVs by 64.58% and 71.27% on average for the first and second architectures respectively, in cost of a negligible overheads in total wire length and auxiliary switches.

Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs

Compared with traditional flow in IC designs, the assignment of the inter-die signals between different dies is an important stage in a die-stacking SiP design. In this paper, given a tolerant spacing rule between two inter-die signals, the crossing constraint between two inter-die signals can be firstly defined for the bonding wires in a die-stacking SiP design with a simplified wiring model [7]. Furthermore, based on the connection constraint on any inter-die signal, the capacity constraint on any assigned pad on dies and the crossing constraint between two inter-die signals, an integer linear programming-based (ILP-based) approach is proposed to assign all the inter-die signals to minimize the total wirelength in a die-stacking SiP design. Compared with Lin’s two-stage approach [4] for some tested examples without a tolerant spacing distance between two inter-die signals in an Euclidean wiring model, the experimental results show that our proposed ILP-based approach increases 4.5% of CPU time and reduces 6.2% of total wirelength to assign all the inter-die signals on the average. Besides that, compared with Yan’s iterative approach [6] for some tested examples without a tolerant spacing distance between two inter-die signals in an Euclidean wiring model, the experimental results show that our proposed ILP-based approach uses reasonable CPU time to reduce 5.3% of total wirelength to assign all the inter-die signals on the average. Compared with Lin’s modified two-stage approach and Yan’s modified iterative approach for some dense tested examples with a tolerant spacing distance between two inter-die signals in a simplified wiring model [7], the experimental results show that Lin’s modified two-stage approach only achieves 95.9% of the assignment ratio on the average, Yan’s modified iterative approach only achieves 96.6% of the assignment ratio on the average and our proposed ILP-based approach uses reasonable CPU time to achieve 100% of the assignment ratio.

A Length Matching Routing Algorithm for Set-Pair Routing Problem

In the routing design of interposer and etc., the combination of a pin pair to be connected by wire is often flexible, and the reductions of the total wire length and the length difference are pursued to keep the circuit performance. Even though the total wire length can be minimized by finding a minimum cost maximum flow in set pair routing problems, the length difference is often large, and the reduction of it is not easy. In this paper, an algorithm that reduces the length difference while keeping the total wire length small is proposed. In the proposed algorithm, an initial routing first obtained by a minimum cost maximum flow. Then it is modified to reduce the maximum length while keeping the minimum total wire length, and a connection of the minimum length is detoured to reduce the length difference. The effectiveness of the proposed algorithm is confirmed by experiments.

Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated Circuits

Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.

Architecture model and resource graph building algorithm for detailed FPGA architecture design

This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays (FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML. This format permits the description of any detailed architecture of hard blocks and channels. Then a general algorithm of building FPGA resource graph is presented. The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system which is developed to enable detailed architecture design. Experimental results show that a maximum of 16.36% reduction in total wirelength and a maximum of 9.34% reduction in router effort can be obtained by making very little changes to detailed architectures, which verifies the necessity and effectiveness of the proposed model.

Nonuniform Multilevel Analog Routing With Matching Constraints

Symmetry, common-centroid, topology-matching, and length-matching constraints are four major routing considerations to improve the performance of an analog circuit. Symmetry constraints are specified to route matched nets symmetrically with respect to some common axes. Common-centroid constraints are also specified to route matched net symmetrically with respect to some common centers. Topology-matching constraints are commonly imposed on critical yet asymmetry nets with the same number of bends, vias, and wirelength. Length-matching constraints are specified to route the nets which have limited resources with the same wirelength. These four constraints can reduce current mismatches and unwanted electrical effects between two critical nets. In this paper, we propose the first work to simultaneously consider the four constraints for analog routing while minimizing total wirelength, bend numbers, via counts, and coupling noise at the same time. We first present a basic integer linear programming (ILP) formulation to simultaneously consider the four constraints for analog routing. Then, a prioritized-constraint-aware routing algorithm is proposed to assist analog designers for assigning the four matching constraints and optimizing routing topologies. Effective reduction techniques are also employed to reduce the numbers of ILP variables and constraints for the two routing algorithms. To further enhance the routing performance, a nonuniform multilevel routing framework is presented and integrated into our routing algorithms. Experimental results show that our approach can obtain better routing results and satisfy all specified routing constraints while optimizing circuit performance.

From Caenorhabditis elegans to the human connectome: a specific modular organization increases metabolic, functional and developmental efficiency.

The connectome, or the entire connectivity of a neural system represented by a network, ranges across various scales from synaptic connections between individual neurons to fibre tract connections between brain regions. Although the modularity they commonly show has been extensively studied, it is unclear whether the connection specificity of such networks can already be fully explained by the modularity alone. To answer this question, we study two networks, the neuronal network of Caenorhabditis elegans and the fibre tract network of human brains obtained through diffusion spectrum imaging. We compare them to their respective benchmark networks with varying modularities, which are generated by link swapping to have desired modularity values. We find several network properties that are specific to the neural networks and cannot be fully explained by the modularity alone. First, the clustering coefficient and the characteristic path length of both C. elegans and human connectomes are higher than those of the benchmark networks with similar modularity. High clustering coefficient indicates efficient local information distribution, and high characteristic path length suggests reduced global integration. Second, the total wiring length is smaller than for the alternative configurations with similar modularity. This is due to lower dispersion of connections, which means each neuron in the C. elegans connectome or each region of interest in the human connectome reaches fewer ganglia or cortical areas, respectively. Third, both neural networks show lower algorithmic entropy compared with the alternative arrangements. This implies that fewer genes are needed to encode for the organization of neural systems. While the first two findings show that the neural topologies are efficient in information processing, this suggests that they are also efficient from a developmental point of view. Together, these results show that neural systems are organized in such a way as to yield efficient features beyond those given by their modularity alone.

English

Power consumed by clocking has taken a major part of the whole design circuit. This paper proposed that reducing the power consumption and area by replacing some flip flops with fewer multi-bit flip-flops without affecting the performance of the original circuit. Various techniques are proposed. First to identify those flip-flops that can be merged. Next a combination table is built to enumerate all possible combinations. Finally, those flip-flops are merged in hierarchical manner. Besides the power reduction minimizing the total wire length is also considered. According to the experimental results clock power can be reduced by 20-30% and the running time can also be reduced

Use of Cordon Wire Tension for Static and Dynamic Prediction of Grapevine Yield

An automated system was used during three growing seasons to monitor the change in tension (Δ<i>T</i>) in the load-bearing wire of a trellis to estimate yield in vineyards. Actual yield varied nearly four-fold among the three study years, but in each year the fruit was uniformly distributed along the length of the wire. The automated sensor detected sequential harvests up to ~12 m to either side of the sensor, or 24 m total wire length, in a nonlinear fashion. Yield was predicted statically from Δ<i>T</i> at the lag phase (<i>L</i>) of berry growth (Δ<i>T</i><i>_L</i>) and dynamically from continuous output of Δ<i>T.</i> Relationships between Δ<i>T</i><i>_L</i> and yield were linear. Estimated yield was not sensitive to the date of Δ<i>T</i><i>_L</i>, within 10 days. In using the ratio between the current year Δ<i>T</i> and that of a specific previous year, the differences between estimated and observed yields depended upon the choice of predictor year(s), where years with similar Δ<i>T</i> were the most accurate. Across an estimation interval of <i>L</i> to harvest, the precision of dynamic estimates was determined by the similarity in the day-to-day shapes of the double-logistic curves of Δ<i>T</i> over time. Due to a catastrophic frost in the second year of the study, an extremely small crop and an uncharacteristic growth curve made it difficult to predict yield either statically or dynamically. In practice, the method requires a grower to collect multiple years of growth curves from which to build a robust linear relationship between Δ<i>T</i><i>_L</i> and yield (static estimates), or to apply an average of multiple years’ Δ<i>T</i> values dynamically.

Length-constrained escape routing of differential pairs

In this paper, given a set of differential pairs (DPs) inside a single chip and the maximum tolerant length difference in a DP, a length-constrained escape routing problem in DPs is formulated. Firstly, the feasible merging connections and the feasible merging grids of all the DPs can be selected to satisfy the given length constraint and avoid routing an acute angle on a wire. Furthermore, based on the observation of the DP escape routing results from industrial boards, all the DPs can be divided into global and local DPs. By using two-phase escape routing, some local DPs can be escaped under the direction constraint and routed by using direct paths in direct escape routing and the unrouted local DPs and the global DPs can be escaped and routed by using obstacle-aware shortest paths in iterative obstacle-aware flow-based escape routing. Compared with Yan׳s escape router [11] and Li׳s escape router [12], the experimental results show that our proposed approach uses a shorter total wirelength under the larger length constraint and reduces 79.6% and 46.8% of the CPU time on the average to achieve 100% escape routability for six tested examples, respectively. Additionally, our proposed approach can obtain length-constrained escape routing results with the avoidance of routing an acute angle under the smaller length constraint for the tested example in the reasonable CPU time.

An Effective Cell Spreading Method for Force-Directed Global Placement

Force-directed placement method for large scale integration physical design is a very effective and fast method to spread the cell uniformly in the placement region. But this kind of method also create large amount of cell overlap in initial placement. In this paper, we present an effective method to cope with cell spreading and add additional force without damaging the wire length. It mainly takes the following method: Firstly, in the prior period of iteration n we keep limit the cell moving distance using a rectangle structure .Because the prior iteration play a decisive role in the final placement quality. Secondly, after the cell relative order determined we can use a new method to compute the weight of additional force to accelerate converge. Thirdly, a strategy called iterative local refinement is added in the well-distributed placement to further reduce the total wire length.

An Effective Cell Spreading Method for Force-Directed Global Placement

Force-directed placement method for large scale integration physical design is a very effective and fast method to spread the cell uniformly in the placement region. But this kind of method also create large amount of cell overlap in initial placement. In this paper, we present an effective method to cope with cell spreading and add additional force without damaging the wire length. It mainly takes the following method: Firstly, in the prior period of iteration n we keep limit the cell moving distance using a rectangle structure .Because the prior iteration play a decisive role in the final placement quality. Secondly, after the cell relative order determined we can use a new method to compute the weight of additional force to accelerate converge. Thirdly, a strategy called iterative local refinement is added in the well-distributed placement to further reduce the total wire length.

Analysis of different legalisation methods for unequal sized recursive Min-cut placement

In this paper, different legalisation methods are examined for a new method of min-cut partitioning for VLSI placement. Traditional min-cut placers divide the given circuit into equal sized sub-circuits at each partitioning level. This paper uses a new partitioning method called unequal sized partitioning in which instead of making the sub-circuits size equal, the size of sub-circuits are made unequal. This paper analyses the placement results to minimize the total wire length of unequal sized partitioning for different legalisation schemes. Firstly an introduction to unequal sized recursive partitioning and legalisation schemes are presented. Then these schemes are applied to MCNC benchmark circuits for different partition ratios ranging from 0.1 to 0.9. The results prove that all the legalisation schemes do not give optimal wire lengths for equal sized partitioning. Each circuit has optimal wire length at different partition ratio for a different legalisation method. Finally this paper suggests the need for unequal sized partitioning which improves the wire length significantly as compared to the conventional equal sized partitioning.

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design

With the increasing complexity of circuit design in recent years, the pin assignment and escape routing problems for field-programmable gate array (FPGA) on a printed circuit board (PCB) have become greatly difficult due to the fast increase in pin count and density. Most existing works only focus on either the FPGA pin assignment problem or the PCB escape routing problem independently, but cannot handle them simultaneously. In this paper, we propose an integer linear programming based method to simultaneously solve the problem of pin assignment and escape routing for FPGA-PCB co-design. Moreover, differential pairs and single-ended signals are handled together optimally to minimize the total wirelength in escape routing. Encouraging experimental results are shown to support our approach showing reduction in the number of PCB routing layers and/or wirelength.

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules

Due to process limitations, wiring rules are imposed on chip layout by foundries. Under nanometer wiring rules, the required separation between two wire ends is dependent on their surrounding wires, and there is a limit on the minimum length of each wire segment. However, traditional shortest path algorithms are not properly designed for these rules. In the paper, we propose a maze routing algorithm, called MANA, capable of finding legal shortest paths under these rules. Experiments with seven industrial cases show that by handling these rules during maze routing, 94% of the violations are prevented on average, and the overall runtime of a commercial router is reduced by 71%. In addition, the total wire length is also reduced by 3% on average.

A Floorplanning Algorithm with Minimum Total Length Wires

A floorplan is employed to represent the placement of modules in VLSI design. Floorplanning is a key step in the design of VLSI systems because it provides the first estimates of performance and cost including placement and routing. In this paper, we show an algorithm1 for initial global routing by the single-sequence (SS). The aim of our algorithm is to get a minimum chip area and the shortest total length of wires where the longest (critical) wire in every net is reduced to a minimum. The experimental results show that the design of placement and routing in floorplanning can be considered simultaneously by our algorithm, the efficiency of automatic layout in VLSI can be raised.