Total Wire Length Research Articles

Homogeneous B0 coil design method for open-access ultra-low field magnetic resonance imaging: A simulation study

A multimodal brain function measurement system integrating functional magnetic resonance imaging (fMRI) and magnetoencephalography (MEG) is expected to be a tool that will provide new insights into neuroscience. To integrate fMRI and MEG, an ultra-low-field MRI (ULF-MRI) scanner that can generate a static magnetic field (B0) with an electromagnetic coil and turn off the B0 during MEG measurements is desirable. While electromagnetic B0 coil has the above advantages, it also has a trade-off between size and the broadness of the magnetic field homogeneity. In this study, we proposed a method for designing a B0 multi-stage circular coil arrangement that determines the number of coils required to maximize magnetic field homogeneity and minimize the total wiring length of the coils. The optimized multi-stage coil arrangement had an external shape of 600 mm in diameter and a maximum height of 600 mm, with an aperture of 600 mm in diameter and 300 mm in height. The magnetic field homogeneity was <100 ppm over a 210 mm diameter spherical volume (DSV). Compared to a previous two coil pairs arrangement with the same magnetic field homogeneity, the diameter was 1/1.9 times smaller, indicating that the newly designed B0 coil arrangement realized a smaller size and wider magnetic field homogeneity.

Design of the transmitter coil used in wireless power transfer system based on genetic algorithm

Performance of the wireless power transfer (WPT) system relies on the physical dimensions of the coupled coil, which should be optimally designed to meet required system performance and reduce the operating cost. This paper presents an optimal design based on genetic algorithm (GA) for the transmitter coil used in wireless power transfer system. Physical parameters of the circular flat spiral coil, including wire’s cross-sectional area, coil’s inner diameter, coil’s outer diameter, coil’s turn number, and space between each turn of the coil are considered. The design objective is to minimize the total wire length required by the coil subjected to both linear and nonlinear constraints. The design process is implemented on MATLAB optimization toolbox which is simple and accurate. The validity of proposed optimal coil design is verified by the experiment, which indicates that total wire length of the optimized coil can be reduced by 5.5 percent compared to the conventional coil without sacrificing the system performance. System efficiency obtained from the optimized coil can be improved up to 8.32 percent.

Fast power density aware three‐dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm

AbstractIn this article, we propose a fast three‐dimensional integrated circuit (3D‐IC) floorplanning method for hard macroblocks that includes a thermal management scheme. It applies a genetic algorithm constituted by an optimal combination of crossover and mutation operations to identify the optimal solution for design variables, namely, total wire length, number of through‐silicon vias (TSVs), and maximum average layer power density. The proposed method additionally makes use of a unique TSV placement scheme that arranges TSVs next to their respective functional blocks. To enable efficient heat transmission to the ambient environment, layers with higher power densities are placed closer to the heat sink. The proposed 3D‐IC floorplanning approach provides the fewest TSVs, the lowest peak temperature, and promising values of wire length within the least amount of computation time. Compared to the recent fast thermal analysis for fixed‐outline 3D‐floorplanning, it generates 13.14% shorter wire length, 39.27% lower peak temperature, and 34.35% lesser number of TSVs on average with significant improvement in computation time, while analyzing GSRC thermal benchmark circuits.

Per-RMAP: Feasibility-Seeking and Superiorization Methods for Floorplanning with I/O Assignment.

The feasibility-seeking approach provides a systematic scheme to manage and solve complex constraints for continuous problems, and we explore it for the floorplanning problems with increasingly heterogeneous constraints. The classic legality constraints can be formulated as the union of convex sets. However, the convergence of conventional projection-based algorithms is not guaranteed when the constraints sets are non-convex, which is the case with unions of convex sets. In this work, we propose a resetting strategy to greatly eliminate the divergence issue of the projection-based algorithm for the feasibility-seeking formulation. Furthermore, the superiorization methodology (SM), which lies between feasibility-seeking and constrained optimization, is firstly applied to floorplanning. The SM uses perturbations to steer the iterates of a feasibility-seeking algorithm to a feasible solution with shorter total wirelength. The proposed algorithmic flow is extendable to tackle various constraints and variants of floorplanning problems, e.g., floorplanning with I/O assignment problems. We have evaluated the proposed algorithm on the MCNC benchmarks. We can obtain legal floorplans only two times slower than the branch-and-bound method in its current prototype using MATLAB, with only 3% wirelength inferior to the optimal results. We evaluate the effectiveness of the algorithmic flow by considering the constraints of I/O assignment, and our algorithm achieves 8% improvement on wirelength.

IEDW: A BIM-based indoor electric distribution wiring algorithm using graph theory and capacity-limited multiple traveling salesman problem solver

Building Information Modeling (BIM) has emerged as a new paradigm for the construction industry. The combination of electric distribution systems design and BIM is the future development trend of architectural design. The traditional electric distribution wiring design based on BIM is mainly carried out manually, which is laborious and error-prone. To cope with this challenge, some studies have proposed explorations of automated BIM wiring design based on graphs in building structures, HAVC, and AEC fields, but few efforts were made on automatic electric distribution wiring. In view of its complicated nature, actual construction factors such as design specifications, wiring costs, etc. should be considered with electric distribution wiring simultaneously. To address this issue, this study proposes a BIM-based automatic indoor electric distribution wiring (IEDW) scheme using graph theory and capacity-limited multiple traveling salesman problem (CMTSP). Firstly, the IEDW sets up the model for design specifications and actual wiring costs with four constraints of specification, cost, installation, and load. Then, a electric distribution wiring heterogeneous graph model is designed to solve both specification and installation constraints. Thirdly, a CMTSP-based algorithm is designed to solve the problem of automatic electric distribution wiring under cost and load constraints. Finally, the performance of IEDW is evaluated on three types of buildings. The experimental results proved that the IEDW can provide a more reasonable wiring solution than manual wiring in terms of circuit balance and total wiring length. Moreover, the IEDW can reduce the wiring cost by 8.8% on average. The proposed IEDW will enhance the efficiency of BIM-based electric systems design and delivery.

Study of Helical Antenna Endowing Short Wire Length and Compact Structure for High-Frequency Operations and Its Exclusive Manufacturing Process

In this paper a study of a helical antenna resonating at high-frequency (HF) band with a very compact structure is reported. The designed antenna's S11 parameter magnitude change with frequency was calculated for different geometrical parameters. For each case, first, only a single parameter was changed. Then for a fair comparison, multiple parameters were changed simultaneously while the total wire length was set to be constant. Also, shifts in resonance frequencies and variations in -10 dB bandwidths were investigated. Our results show that resonance behaviour changes distinctively with the geometrical parameters and it allows shortening of the antenna wire length. For the designed antenna, the resonances shift to lower frequencies and -10 dB bandwidths around the resonances decrease as the winding wire thickness, number of turns, and turn radius increase. Whereas as the turn spacing increases the resonances shift to higher frequencies and -10 dB bandwidths widen, although the total wire length of the antenna increases. To verify the simulation results, the designed antenna was fabricated with an exclusive manufacturing process and characterized. The measurement results are in good agreement with the simulation results. It demonstrates the feasibility of the proposed manufacturing technique, which is new in the literature and enables accurate and rigid antenna fabrication with simple and low-cost steps.

NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact

Nanosheet FETs (NSFETs) are attracting attention as promising devices that can replace FinFETs beyond the 5-nm node. Despite the importance of the devices, few studies analyze the impact of NSFETs at the block-level. In this article, we introduce NS3K, the first 3-nm NSFET standard cell library, and examine the results on a block-level scale. In addition to the overall process of designing a full library, we extended the scope of the buried power rail (BPR) to better layout designs. We showed that BPR, originally proposed to overcome power delivery problems, is also an effective solution for standard cell hegith reductions. Using BPR, we highlight that 4-track height standard cell designs have a negligible impact on power delivery and signal routing. Overall chip results show that the 3-nm NSFET outperforms the 5-nm FinFET by −27.4% in power, −25.8% in total wirelength, −8.5% in the number of cells, −47.6% in area, and 34.7% performance, respectively, owing to better device performance and interconnect scaling. However, careful device/layout designs and new interconnect structures must be applied to continue the scaling trend and maximize the advantages of 3-nm technology.

Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process

Complementary field-effect transistor (CFET) is a future transistor type with a high potential to be used beyond 3-nm technology nodes. Despite its high future value, studies related to CFETs mostly focused on the device aspects. In other words, the path of CFET full-chip IC design is not fully demystified, knowing that various design factors/steps (such as schematic, layout, parasitics, design flow) must be considered on top of device traits for full-chip level IC. Therefore, this study focuses on enlightening the remaining factors/steps for full-chip IC design. In detail, we notify the importance of parasitics from various aspects of CFET design and provide optimization solutions. Compared to nanosheet FET (NSFET) on the full-chip scale, CFET shows a reduction of the area by −48.2%, power by −29.4%, total wirelength by −32.5%, and the number of cells by −18.1%.

Nonoptimal component placement of the human connectome supports variable brain dynamics

Abstract Neural systems are shaped by multiple constraints, balancing region communication with the cost of establishing and maintaining physical connections. It has been suggested that the lengths of neural projections be minimized, reducing their spatial and metabolic impact on the organism. However, long-range connections are prevalent in the connectomes across various species, and thus, rather than rewiring connections to reduce length, an alternative theory proposes that the brain minimizes total wiring length through a suitable positioning of regions, termed component placement optimization. Previous studies in nonhuman primates have refuted this idea by identifying a nonoptimal component placement, where a spatial rearrangement of brain regions in silico leads to a reduced total wiring length. Here, for the first time in humans, we test for component placement optimization. We show a nonoptimal component placement for all subjects in our sample from the Human Connectome Project (N = 280; aged 22–30 years; 138 females), suggesting the presence of constraints—such as the reduction of processing steps between regions—that compete with the elevated spatial and metabolic costs. Additionally, by simulating communication between brain regions, we argue that this suboptimal component placement supports dynamics that benefit cognition.

Experimental Study on Structural Behaviour of Steel Wire Mesh under Impact Loading

In view of application to debris flow/rockfall barrier system, several types of steel wire mesh were selected to verify their basic behaviour under impact load of free fall weight at the controlled testing environment at an in-house testing facility capable of dropping a heavy weight on approximately 1-meter square panel made of such steel wire mesh material. Out of the 3 types of wire mesh tested, high-performance chain link endured the highest impact load energy, while newly developed wire mesh showed a high potential of effectively absorbing the impact energy by its plastic deformation along the total length of wire components. Both of the above two types of wire mesh are expected to be applied in flexible type debris flow catchment system in combination with larger opening mesh such as ring net. The newly developed wire mesh consisting of spirally deformed steel wires behaved as energy-absorbing elements while transmitting the impact load to the supporting ropes by its own plastic deformation along the total wire length.

Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings

This article presents a new paradigm for analog placement, which further incorporates poles in addition to the considerations of symmetry island and monotonic current flow while minimizing wire crossings. The nodes along the signal paths in an analog circuit contribute to the poles, and the parasitics on these dominant poles can significantly limit the circuit performance. Although the monotonic placement methods introduced in the previous works can generate simpler routing topologies, the unawareness of poles, especially the dominant and the first non-dominant poles and wire crossings among critical nets, may increase wire load and performance degradation. This article proposes a pole-aware analog layout synthesis methodology to minimize the total wire load and wire crossings while satisfying different symmetry and topological routing constraints. Using a strong-connectivity approach to the group Steiner problem, the presented method for automatic selection of port locations can help reduce total wirelength, increase routing flexibility, and minimize total wire crossings. Experimental results show that the proposed approach results in better solution quality in circuit performance compared with other recent works.

VLSI Placement Optimization Algorithms

Placement is a fundamental optimization step to compute cell locations. The quality of results in Clock Tree Synthesis (CTS) and routing stages is impacted by the placement solution. The placement optimization flow is split into (1)global placement, (2) legalization, and (3) detailed placement. In global placement, cell locations are computed to minimize total wire length subject to a maximum cell density threshold. The cell overlapping and cell alignment to site row boundaries are relaxed. In legalization, cells are placed in locations free of overlapping and aligned to site row boundaries. Legalization algorithms compute cell locations with minimized cell displacement. In detailed placement, objectives are optimized locally. Detailed placement algorithms iterate over one cell or a small set of cells. The traditional optimization objective is total wire length. Placement algorithms also address timing violations, routability, design rules, and so forth. The placement algorithms rely on heuristics and formal methods to compute optimized cell locations. Moreover, placement algorithms require models to address signal delay propagation, area density, routing congestion, hyper-edge nets, and so forth. In the literature, several algorithms have been presented to improve placement solutions. On the other hand, placement is a really challenging problem that continues to have space for further improvement and for innovative algorithms.

Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints

Mixed-cell-height standard cells are prevailingly used in advanced technologies to achieve better design tradeoffs among timing, power, and routability. As feature size decreases, the placement of cells with multiple threshold voltages may violate the complex minimum-implant-area (MIA) layer rule arising from the limitations of patterning technologies. Existing works consider the mixed-cell-height placement problem only during legalization or handle the MIA constraints during detailed placement. In this article, we address the mixed-cell-height placement problem with MIA constraints in two major stages: 1) post-global placement (Post-GP) and 2) MIA-aware legalization. In the Post-GP stage, we first present a continuous and differentiable cost function to address the Vdd/Vss alignment constraints and add weighted pseudonets to MIA-violation cells dynamically. Then, we propose a proximal optimization method based on the given global placement result to simultaneously consider Vdd/Vss alignment constraints, MIA constraints, cell distribution, cell displacement, and total wirelength. In the MIA-aware legalization stage, we develop a graph-based method to cluster cells of specific threshold voltages and apply a strip-packing-based binary linear programming to reshape cells. Then, we propose a matching-based technique to resolve intrarow MIA violations and reduce filler insertion. Furthermore, we formulate inter-row MIA-aware legalization as a quadratic programming problem, which is efficiently solved by a modulus-based matrix splitting iteration method. Finally, MIA-aware cell allocation and refinement are performed to further improve the result. Experimental results show that without any extra area overhead, our algorithm still can achieve 5.4% shorter final total wirelength than the state-of-the-art work.

Performance-Driven X-Architecture Routing Algorithm for Artificial Intelligence Chip Design in Smart Manufacturing

The new 7-nm Artificial Intelligence (AI) chip is an important milestone recently announced by the IBM research team, with a very important optimization goal of performance. This chip technology can be extended to various business scenarios in the Internet of Things. As the basic model for very large scale integration routing, the Steiner minimal tree can be used in various practical problems, such as wirelength optimization and timing closure. Further considering the X-architecture and the routing resources within obstacles, an effective performance-driven X-architecture routing algorithm for AI chip design in smart manufacturing is proposed to improve the delay performance of the chip. First, a special particle swarm optimization algorithm is presented to solve the discrete length-restricted X-architecture Steiner minimum tree problem in combination with genetic operations, and a particle encoding scheme is presented to encode each particle into an initial routing tree. Second, two lookup tables based on pins and obstacles are established to provide a fast information query for the whole algorithm flow. Third, a strategy of candidate point selection is designed to make the particles satisfy the constraints. Finally, a refinement strategy is implemented to further improve the quality of the final routing tree. Compared with other state-of-the-art algorithms, the proposed algorithm achieves a better total wirelength, which is an important index of performance, thus better satisfying the demand for delay performance of AI chip design in smart manufacturing.

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits With Maximum Path Length Consideration

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal that incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point that renders the conventional design flow of placement followed by clock tree synthesis (CTS) ineffective to obtain a high quality clock tree with low clock skew. Moreover, very few works in the literature attempted to minimize the maximum path length during SFQ circuit placement. The maximum path length, which is the length of the longest source-to-sink path of any data signal, should be minimized to achieve a higher final performance and to reduce the overhead for length matching in subsequent routing. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by CTS and clock splitter insertion, and then, performs a second stage of global placement to replace both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is resynthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. We propose a novel net model in global placement that facilitates the concurrent optimization of the total wirelength and the maximum path length. After legalizing the placement of all cells, a specialized placement refinement method is run to further reduce the clock skew and the maximum path length. Compared with the previous state-of-the-art work, on average, we reduced the total half-perimeter wirelength by 9%, reduced the maximum path length by 58%, and reduced the clock skew by 32%.

Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios

Standard-cell placement is the fundamental step in a typical VLSI/ASIC design flow. Its result, paired with the outcome of the routing procedure can be the decisive factor in rendering a design manufacturable. Global placement generates an optimized instance of the design targeting a set of metrics, while ignoring rules pertaining its feasibility. Legalization and detailed placement rectify this situation, attempting to attain minimum quality loss by often disregarding the connectivity between cells and making runtime the focal point of these steps. In this article, we present a set of variations on a connectivity-based legalization scheme that can either be applied as a legalizer or a detailed placer. The variations can be applied in the entirety of the chip area or in the confinement of a user-specified bin while they are guided by various optimization goals, e.g., total wire length, displacement and density. We analytically describe our variations and evaluate them through extensive simulations on commonly used benchmarks.

An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning

Floorplanning is an ever-emerging field in the Very Large Scale Integration (VLSI) circuit design automation since it deals with essential design metrics of a floorplan, such as chip area, total wirelength, and temperature. This paper aims to optimize these design metrics to obtain an optimal floorplan with reduced computation time. A Skewed B* (SKB) tree based Enhanced Memetic Algorithm (EMA) is proposed for temperature-driven fixed-outline non-sliceable floorplanning. The proposed EMA has two search phases: a global search based on Genetic Algorithm (GA), and a local search based on the Adaptive Fast Simulated Annealing (AFSA) algorithm. A novel dynamic threshold bias search strategy is implemented to balance the search phases, thus increasing the convergence speed to obtain an optimal solution. The performance of the proposed algorithm is tested on MCNC (Microelectronic Centre for North Carolina), and GSRC (Gigascale System Research Centre) state-of-the-art benchmark circuits. Experimental results show that the EMA produces highly optimal design metrics on all tested benchmark circuits.

Wiring minimization of deep neural networks reveal conditions in which multiple visuotopic areas emerge

The visual system is characterized by multiple mirrored visuotopic maps, with each repetition corresponding to a different visual area. In this work we explore whether such visuotopic organization can emerge as a result of minimizing the total wire length between neurons connected in a deep hierarchical network. In particular we ask, given N neurons with a given connectivity and a 2-d grid with N locations, how will the neurons be placed on the grid such that the total distance between the connected neurons is minimized? This problem is an NP-hard combinatorial problem which we solve using simulated annealing. We first construct multi-layer feedforward hierarchical networks, and examine how different parameters of the network such as filter size, number of channels, and stride affect the placement of the neurons on the grid. By introducing visual input to the network we can visualize the resulting visuotopic organization on the 2-d grid. Our results show that networks with purely feedforward connectivity typically result in a single visuotopic map, and in certain cases no visuotopic map emerges. However, when we modify the network by introducing lateral connections, with sufficient lateral connectivity among neurons within layers, multiple visuotopic maps emerge, where some connectivity motifs yield mirrored alternations of visuotopic maps–a signature of biological visual system areas. These results demonstrate that different connectivity profiles have different emergent organizations under the minimum wiring hypothesis, and highlight that characterizing the large-scale spatial organizing of tuning properties in a biological system might also provide insights into the underlying connectivity.

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Multirow Complementary-FET (CFET) Standard Cell Synthesis Framework Using Satisfiability Modulo Theories (SMTs)

With the relentless scaling of technology nodes, the track number reduction of conventional (Conv.) cell is starting to reach its limitations due to limited routing resources, lateral p-n separations, and performance requirements. As a result, to exploit the benefits of 3-D architectures, complementary-FET (CFET) technology, which stacks P-FET on N-FET or vice versa, is proposed to release the restriction of p-n separation and reduce in-cell routing congestion by enabling p-n direct connections. However, CFET standard cell (SDC) synthesis demands a holistic reconsideration of multirow (MR) structure to maximize the cell and block-level area benefits due to limited in-cell routing tracks and routability that comes from the stacked structure and reduced cell height. In this article, we propose a satisfiability modulo theory (SMT)-based MR CFET SDC synthesis framework that simultaneously solves place-and-route to minimize the cell area by considering single-row and MR placement together. We enable explorations on upper/lower M0A/PC routing to leverage the shared-and-split structure across cell rows with the proposed MR dynamic complementary pin allocation scheme. We demonstrate that MR 2.5T CFET without and with upper/lower M0A/PC routing achieves 16.44% and 20.61% on the average reduced cell areas, respectively, compared to 3.5T CFET. Moreover, MR 2.5T CFET SDCs achieve 13.43% and 14.40% less block-level area and total wirelength on average compared to 3.5T CFET SDCs.