Total Transistor Count Research Articles

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design.

A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.

Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations

Design methodology for ultrahigh-speed 5-2 and 7-2 compressors has been illustrated in this article. With the help of introduced procedure, the gate-level delay has been reduced considerably when compared with the previous designs, while the total transistor and gate count remain in a reasonable range. By starting the discussion for the carry rippling problem in n - 2 compressors, the method has been developed for 5-2 compressor and is expanded for 7-2 architecture, which shows 32% and 30% improvement in speed performance for these structures, respectively. Also, the careful design considerations have been taken into account to keep other characteristics, such as power and active, are at a reasonable level. Moreover, for a fair comparative conclusion, the best-reported circuits have been redesigned, and their parasitic elements were extracted utilizing the same technology employed for the synthesis of the proposed circuits. Finally, a typical 16 × 16 bit multiplier has been implemented to investigate the efficiency of the designed compressor blocks. Based on the postlayout simulation results provided using HSPICE for TSMC 0.18-μm standard CMOS technology and 1.8-V power supply, the proposed compressors demonstrate better speed performance and power-delay product (PDP) factor over previous works. As the results depict, the delay of 303 ps has been achieved for the 5-2 compressor while the measured delay of the designed 7-2 compressor is 464 ps.

A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit

One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque (STT) switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed, high endurance, CMOS compatibility and mainly the low power dissipation which can offer the solutions for the problems posed by existing CMOS technology. We have proposed a novel logic-in-memory (LIM) architecture of magnetic arithmetic logic unit (P-MALU) based on hybrid STT-MTJ/CMOS circuits. Simulation results reveal that there is significant reduction in the total power dissipation and transistor count of arithmetic unit by 28.44% and 29.16% compared to double pass transistor logic based clocked CMOS ALU design (DPTL-C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS-ALU), while 58.87% and 45.16% to modified magnetic arithmetic logic unit (M-MALU) respectively. Reduction in average power dissipation for logical unit is 37.61% and 52.55% along with 47.22% and 42.42% fewer transistors than DPTL-C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS-ALU and M-MALU design respectively. Monte-Carlo(MC) simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ, to study the behavior of DPTL-C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS-ALU, M-MALU and P-MALU designs in terms of power dissipation. All the simulation results reveal that the P-MALU is superior than other two ALU designs in terms of power dissipation, delay and device count. Further, the P-MALU circuit is extended for 4-bits arithmetic operations. Electrical simulations are performed to verify the functionality of the design for higher bit operations which demonstrates the feasibility of the proposed design in VLSI circuits.

Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique

One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed performance. For the reduction of static power, two types of stacking called series and forced transistor stacking are applied. The circuits are simulated using Cadence Virtuoso in 45[Formula: see text]nm CMOS technology with a power supply of 1[Formula: see text]V at 500[Formula: see text]MHz when input switching activity is 25%. The simulated results indicated that the new designs (TCRFF, S-TCRFF and FST in TCRFF) excelled in different circuit performance indices like Power-Delay-Product (PDP), Energy-Delay-Product (EDP), average and leakage power with less layout area compared with the performance of nine recently proposed FF designs. The improvement in PDPdq value was up to 89.2% (TCRFF), 89.9% (S-TCRFF) and 90.3% (FST in TCRFF) with conventional transmission gate FF (TGFF).

An Efficient O( $N$ ) Comparison-Free Sorting Algorithm

In this paper, we propose a novel sorting algorithm that sorts input data integer elements on-the-fly without any comparison operations between the data—comparison-free sorting. We present a complete hardware structure, associated timing diagrams, and a formal mathematical proof, which show an overall sorting time, in terms of clock cycles, that is linearly proportional to the number of inputs, giving a speed complexity on the order of O(N). Our hardware-based sorting algorithm precludes the need for SRAM-based memory or complex circuitry, such as pipelining structures, but rather uses simple registers to hold the binary elements and the elements’ associated number of occurrences in the input set, and uses matrix-mapping operations to perform the sorting process. Thus, the total transistor count complexity is on the order of O(N). We evaluate an application-specified integrated circuit design of our sorting algorithm for a sample sorting of N = 1024 elements of size K = 10-bit using 90-nm Taiwan Semiconductor Manufacturing Company (TSMC) technology with a 1 V power supply. Results verify that our sorting requires approximately 4– $6~\mu \text{s}$ to sort the 1024 elements with a clock cycle time of 0.5 GHz, consumes 1.6 mW of power, and has a total transistor count of less than 750 000.

Novel low-cost and fault-tolerant reversible logic adders

In recent years, reversible logic circuits have received considerable attention due to their diverse applications in various fields. As the computing systems are susceptible to different environmental effects which can impact their intended operations, having the fault-tolerance capability is of great importance. In this paper, at first, a novel reversible gate is presented to achieve a parity preserving full adder which serves as the main building block of different adders. Further on, by using the proposed full adder and new arrangements of other reversible gates, some new low-cost fault-tolerant adders including binary coded decimal, carry skip and carry look-ahead architectures are presented. The new adders are highly efficient in the quantum cost, total logical calculation and transistor count compared to the existing designs. In addition, regarding other factors including the number of gates, garbage outputs and maximum delay, they are the best or among the favorite parity preserving reversible adders.

A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving

An extremely low-power flip-flop (FF) named topologically-compressed flip-flop (TCFF) is proposed. As compared with conventional FFs, the FF reduces power dissipation by 75% at 0% data activity. This power reduction ratio is the highest among FFs that have been reported so far. The reduction is achieved by applying topological compression method, merger of logically equivalent transistors to an unconventional latch structure. The very small number of transistors, only three, connected to clock signal reduces the power drastically, and the smaller total transistor count assures the same cell area as conventional FFs. In addition, fully static full-swing operation makes the cell tolerant of supply voltage and input slew variation. An experimental chip design with 40 nm CMOS technology shows that almost all conventional FFs are replaceable with proposed FF while preserving the same system performance and layout area.

A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

Design and analysis of a compact fast parallel multiplier for high speed DSP applications using novel partial product generator and 4 : 2 compressor

Parallel multiplier is one of the most important building blocks in all the DSP processors, which needs faster computations. To reduce the total transistor count in a multiplier we have proposed two new approaches. The first approach is using a 26 transistor booth encoder and a 8-transistor/partial-product booth selector to generate partial products. The second approach proposes a new circuit for 4 : 2 compressors. The booth encoder and booth selector reported here are the smallest in transistor count, but comparable to the best delay with less power consumption. This paper describes a comparison of a compact 16 × 16 parallel multiplier using the new circuit components. This shows a transistor count advantage of 27% and 52% in partial product generation and partial product accumulation, respectively.

A static differential double edge-triggered flip–flop based on clock racing

In this paper, a double edge-triggered (DET) flip–flop is proposed, suitable for high-performance and low-power applications. The presented flip–flop has differential structure and provides static operation. The double edge triggering operation is achieved, by generating a narrow pulse immediately after each clocking edge, which is used to set the flip–flop in the transparent phase. The narrow pulse generation technique is based on a clock racing methodology. Compared to existing DET flip–flops, the proposed DET flip–flop results in significant delay and power gains, but keeps the total transistor count low. By applying the narrow pulse to more than one similar adjacent DET flip–flops, we can further reduce the power and the transistor count.

A Single Electron Neuron Device

A neuron device utilizing the single electron tunneling (SET) effect is described. The device consists of four parts: synaptic weight circuits, a multiplier, an adder, and a nonlinear activation function circuit. The synaptic weight memory is designed with only two turnstiles, and the multiplier and the nonlinear activation function are realized with the use of single electron inverter circuits. The total SET transistor count of a neuron with n inputs is only 6n+2, which is an advantage over a neuron consisting of conventional complementary metal-oxide semiconductor (CMOS) transistors from the viewpoint of occupation area and consumption power. Due to the smallness of the SET neuron, large systems of artificial neural networks could be realized with the use of these devices.

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders

A 54/spl times/54-b multiplier with only 60 K transistors has been fabricated by 0.25-/spl mu/m CMOS technology. To reduce the total transistor count, we have developed two new approaches: sign-select Booth encoding and 48-transistor 4-2 compressor circuits both implemented with pass transistor logic. The sign-select Booth algorithm simplifies the Booth selector circuit and enables us to reduce the transistor count by 45% as compared with that of the conventional one. The new compressor reduces the count by 20% without speed degradation. By using these new circuits, the total transistor count of the multiplier is reduced by 24%. The active size of the 54/spl times/54-b multiplier is 1.04/spl times/1.27 mm and the multiplication time is 4.1 ns at a 2.5-V power supply.

VLSI systolic binary tree-searched vector quantizer for image compression

A high-speed image compression VLSI processor based on the systolic architecture of difference-codebook binary tree-searched vector quantization has been developed to meet the increasing demands on large-volume data communication and storage requirements. Simulation results show that this design is applicable to many types of image data and capable of producing good reconstructed data quality at high compression ratios. Various design aspects of the binary tree-searched vector quantizer including the algorithm, architecture, and detailed functional design are thoroughly investigated for VLSI implementation. An 8-level difference-codebook binary tree-searched vector quantizer can be implemented on a custom VLSI chip that includes a systolic array of eight identical processors and a hierarchical memory of eight subcodebook memory banks. The total transistor count is about 300000 and the die size is about 8.67/spl times/7.72 mm/sup 2/ in a 1.0 /spl mu/m CMOS technology. The throughput rate of this high-speed VLSI compression system is approximately 25 Mpixels per second and its equivalent computation power is 600 million instructions per second.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Modular Set of Analog Microcircuits Intended for Satellite Experiments

A set of four modular building block elements have been designed for use in a variety of satellite experiments. These elements comprise an amplifier, a zero crossing discriminator, a linear gate and a pulse shaper. The circuits are constructed in hybrid form using discrete transistors and tantalum thin film resistors on ceramic substrates. This form of construction was dictated by considerations of radiation damage, component tolerances and power consumption. An attempt has been made to design the elements so that they can be used in a variety of ways. Individual examples of these applications are given in the context of a particular space experiment. This experiment involves the use of a multielement semiconductor detector telescope and employs approximately 100 of the analog building blocks. The total transistor count is approximately 500 and the power consumption is less than 1.5 watts.