Total Ionizing Dose Effects Research Articles

Radiation-tolerance analysis of I-gate n-MOSFET according to isolation oxide module in the CMOS bulk process

The n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET) produced in the widely used CMOS bulk process takes radiation damage by the total ionizing dose (TID) effects in radiation environments, so the radiation-tolerant properties of semiconductor integrated-circuits (ICs) used in high-radiation environments is a critical issue. The formation method of the isolation oxide module (IOM), which induces the radiation-induced leakage currents, differs depending on the chip density of the CMOS bulk process. In this paper, we designed and fabricated I-gate n-MOSFETs for bulk process and analyzed the radiation-tolerant characteristics according to IOM. The I-gate n-MOSFET chips are fabricated using the shallow trench isolation (STI) 0.18um and local oxidation of silicon (LOCOS) 0.35um processes of the CMOS bulk process. Tests and evaluation of the TID effects on the chips are carried out by irradiating a total cumulative dose up to 2 Mrad(Si). As the results, in the standard n-MOSFET, the leakage currents of the LOCOS and STI processes are 27.7uA and 16.4uA, and in I-gate n-MOSEFT, are 1.1uA and 0.7uA. The leakage currents of standard n-MOSFET increased by about 25 times before and after irradiation, but the electric characteristics of I-gate n-MOSFET is maintained regardless of the process. Therefore, the process versatility of the I-gate n-MOSFET with the radiation-tolerant performance has been verified.

Total ionizing dose effects in pinned photodiode complementary metal-oxide-semiconductor transistor active pixel sensor**Project supported by the National Natural Science Foundation of China (Grant No. 11675259) and the West Light Foundation of the Chinese Academy of Sciences (Grant Nos. 2016-QNXZ-B-8 and 2016-QNXZ-B-2).

A pinned photodiode complementary metal–oxide–semiconductor transistor (CMOS) active pixel sensor is exposed to 60Co to evaluate the performance for space applications. The sample is irradiated with a dose rate of 50 rad (SiO2)/s and a total dose of 100 krad (SiO2), and the photodiode is kept unbiased. The degradation of dark current, full well capacity, and quantum efficiency induced by the total ionizing dose damage effect are investigated. It is found that the dark current increases mainly from the shallow trench isolation (STI) surrounding the pinned photodiode. Further results suggests that the decreasing of full well capacity due to the increase in the density, is induced by the total ionizing dose (TID) effect, of the trap interface, which also leads to the degradation of quantum efficiency at shorter wavelengths.

Constant voltage stress characterization of nFinFET transistor during total ionizing dose experiment

During the lifetime of integrated circuits in the space environment, they encounter radiation degradation, such as the total ionizing dose (TID) effect as well as intrinsic degradation mechanisms, such as the constant voltage stress (CVS) effect. This paper analyzes the effects of TID and CVS on the nFinFET with a high-κ (HfO2) metal gate (HKMG). Various dimensions and stress voltages on nFinFETs are characterized under room temperature. Experimental results show that both effects can cause the threshold voltage (Vth) of the transistor to shift towards positive. Compared with TID-induced degradation, the devices appear relatively robust against CVS.

Process variation dependence of total ionizing dose effects in bulk nFinFETs

The electrical characteristics of bulk nFinFETs after total-ionizing-dose (TID) irradiation were experimentally evaluated with respect to the process variation (PV). The inconsistent transfer characteristics, particularly the different threshold voltage shifts under an identical bias condition and irradiation dose, were investigated through technology computer aided design (TCAD) simulation, considering the shallow trench isolation (STI) footing and the asymmetrical sidewall. The influence that the bias condition had, as an important factor including ON, OFF, and transmission gate (TG), is included in this paper to better illustrate the PV dependence. The HfO2 high-ĸ metal gate, the STI, and the PV dependent geometry were some of the influences that occurred within the degradation of electrical performances as the TID increased. A radiation-hardness strategy was proposed in order to improve the electrical properties of the FinFET devices in the radiation environments.

Total Ionizing Dose Effects on a Delay-Based Physical Unclonable Function Implemented in FPGAs

Physical Unclonable Functions (PUFs) are hardware security primitives that are increasingly being used for authentication and key generation in ICs and FPGAs. For space systems, they are a promising approach to meet the needs for secure communications at low cost. To this purpose, it is essential to determine if they are reliable in the space radiation environment. In this work we evaluate the Total Ionizing Dose effects on a delay-based PUF implemented in SRAM-FPGA, namely a Ring Oscillator PUF. Several major quality metrics have been used to analyze the evolution of the PUF response with the total ionizing dose. Experimental results demonstrate that total ionizing dose has a perceptible effect on the quality of the PUF response, but it could still be used for space applications by making some appropriate corrections.

X-Ray and Proton Radiation Effects on 40 nm CMOS Physically Unclonable Function Devices

Total ionizing dose effects are investigated on a physically unclonable function (PUF) based on CMOS breakdown. Devices irradiated to 2 Mrad(SiO2) show less than 11% change in current ratio at 1.2 V. The read-out window of programmed PUFs decreases significantly at high-dose proton irradiation, and then recovers back to the original value after annealing. The proton test results for the pFET selector, the unbrokennFET, and the brokennFET indicate that the threshold-voltage shift of the pFET selector contributes mainly to the degradation of the PUF.

Evolution of Total Ionizing Dose Effects in MOS Devices With Moore’s Law Scaling

The general reduction in the thicknesses of critical dielectric layers driven by Moore’s law scaling has led to increasingly more manageable total-ionizing-dose (TID) response over the last ~50 years. Effects of oxide, interface, and border traps in MOS gate oxides on TID response are now mostly well known for SiO2 gate dielectrics, and the leakage currents due to isolation oxides can be conservatively bounded with existing test methods. Radiation hardened and/or radiation-tolerant technologies have been developed that can survive doses that exceed 1 Mrad(SiO2). Advances in computing technology enabled by Moore’s law scaling and concomitant enhancements in computational techniques have greatly facilitated the modeling and simulation of TID effects in microelectronic devices and ICs. However, the TID response of nanoscale MOS devices with advanced gate stacks and high- ${K}$ gate dielectrics, and/or alternative materials to Si, is often more complex than for MOS devices with SiO2 gate oxides. TID challenges remain for linear bipolar technologies that exhibit enhanced low-dose-rate sensitivity and for microelectronic devices that must function at doses above ~100 Mrad(SiO2), e.g., in high luminosity accelerator environments. TID effects have also recently been observed in wide bandgap semiconductor devices (e.g., GaN/AlGaN HEMTs) with no gate oxide.

Total ionizing dose effects on the SOI pixel sensor for X-ray astronomical use

We report on total ionizing dose effects on the X-ray SOI pixel sensor, XRPIX. XRPIX has been developed as an imaging spectrometer for X-ray astronomical use in space. Front- and back-illuminated (FI and BI) devices were irradiated with hard X-rays from an X-ray tube operated at 30 kV with a Molybdenum target. We found that the degradation rate of the readout noise of the BI device was approximately three times slower than that of the FI device as a function of radiation exposure. Those of both type of devices, however, were virtually identical when the readout noise was evaluated as a function of the absorbed dose at the buried oxide layer, DBOX. The pedestal and analog-to-digital conversion gain also displayed similar tendencies. These results demonstrate that BI type devices have a higher radiation tolerance as a focal plane sensor of an X-ray mirror and the radiation tolerance of XRPIX devices is governed by DBOX. The readout noise was stable up to about 1 krad in DBOX, increased by about 10% at 10 krad in DBOX, and continued to increase under further irradiation. If we employ an X-ray mirror with a half-power diameter of 10 arcsec and a focal length of 10 m, 10 krad in DBOX, a reasonable threshold of radiation tolerance in this experiment, is equivalent to more than three years in orbit, typically required of space-borne sensors.

P-MOSFET latch-based monolithic signal-processing circuit for nuclear event detector

This paper presents a p-MOSFET latch-based nuclear event detector signal-processing circuit which is implemented using a commercial standard 0.35-μm CMOS process. A positive-feedback loop consisting of a p-MOSFET with a common-source configuration and a photocurrent compensation MOSFET are used to offset the transient radiation effects. Additionally, a timer circuit containing an on-chip timer capacitor serves to reduce the response time. To mitigate the total ionizing dose effect, all n-MOSFETs are laid out using dummy gate-assisted n-MOSFETs.The measured response time of the fabricated chip is 12.2 ns. After measuring the electrical characteristics of the fabricated chip, the chip is exposed to 60Co gamma rays at a dose of 1.14 Mrad (Si). Even after exposure to radiation, the performance of the irradiated chip is nearly identical to that of a non-irradiated chip. To evaluate the upset threshold with regard to the dose rate of the fabricated chip, the chip is also exposed to prompt gamma rays with different dose rates, and the measured dose rate upset threshold is found to exceed 1.9×107rad(Si)/s.

Total Ionizing Dose Effects of 55-nm Silicon-Oxide-Nitride-Oxide-Silicon Charge Trapping Memory in Pulse and DC Modes**Supported by the National Natural Science Foundation of China under Grant No 616340084, the Youth Innovation Promotion Association of Chinese Academy of Sciences under Grant No 2014101, and the Austrian-Chinese Cooperative R&D Projects of International Cooperation Project of Chinese Academy of Sciences under Grant No 172511KYSB20150006.

The 60Co-γ ray total ionizing dose radiation responses of 55-nm silicon-oxide-nitride-oxide-silicon (SONOS) memory cells in pulse mode (programmed/erased with pulse voltage) and dc mode (programmed/erased with direct voltage sweeping) are investigated. The threshold voltage and off-state current of memory cells before and after radiation are measured. The experimental results show that the memory cells in pulse mode have a better radiation-hard capability. The normalized memory window still remains at 60% for cells in dc mode and 76% for cells in pulse mode after 300 krad(Si) radiation. The charge loss process physical mechanisms of programmed SONOS devices during radiation are analyzed.

Radiation hardness of silicon-on-insulator pixel devices

Silicon-on-Insulator (SOI) CMOS is an attractive technology because of pixel sensor applications for its inherent advantages such as superior isolation of each FET by the surrounding insulator. We have been developing SOI pixel devices since 2005 using the FD-SOI technology and noticed that the insulator layers impose significant sensitivity to the total ionization dose (TID) effect. Research activities in the last ten years to improve radiation hardness are reviewed, such as introduction of buried wells and double SOI wafers.

LOW DOSE RATE EFFECTS IN SILICON BASED DEVICES AND INTEGRATED CIRCUITS: A REVIEW

This paper is a review on total ionizing dose effects in silicon semiconductor devices and integrated circuits under low dose rate irradiation that is typical of space applications. We consider the mechanism of radiation induced charge buildup in the dielectric of MOS structures and at the semiconductor/dielectric interface; in addition, the paper reports an analysis of the nature of defects in Si/ SiO2 structure which are responsible for these processes. Also, the paper describes specific features of annealing of the charge trapped in dielectric and interface traps. The degradation of MOS and bipolar devices is considered for low dose rate irradiation conditions inherent to space application. We show that under low dose rate irradiation MOS devices are susceptible to time−dependent effects which are determined by the kinetics of charge buildup and annealing in the Si/SiO2 structure, while bipolar devices may be susceptible to true dose rate effects. The paper considers basic experimental modeling methods for low dose rate effects during accelerated testing of silicon devices and integrated circuits. We show that it is necessary to use essentially different experimental approaches for the modeling of time−dependent effects in MOS devices and true dose rate effects in bipolar devices and integrated circuits.

Total Ionizing Dose Effects of SiGe HBTs Induced by 60Co Gamma-Ray Irradiation

For evaluating the SiGe heterojunction bipolar transistors (HBTs) performance during and after gamma-ray irradiation, the characteristics of the direct current (dc) gain of the test samples changed with increasing irradiation dose, and collector current injection levels during 60Co gamma irradiation were measured and analyzed. The experimental results of the typical dc and alternating current (ac) electronic parameters before and after irradiation revealed that the base current Ib, the collector current IC, the dc current gain, and the maximum oscillation frequency fmax exhibited degradation. While other electronic parameters including the cut-off frequency fT, the ac current gain |H21|, and output capacitance CBC did not exhibit any significant change compared with those of pre-irradiation. The degradation mechanisms of the typical dc and ac parameters measured in this work were primarily analyzed. The tested results of SiGe HBTs offered some reference data for evaluating the behavior of the test type of device operated in an ionizing radiation environment.

Analysis of Total Ionizing Dose effects for highly scaled CMOS devices in Low Earth Orbit

Abstract Total Ionizing Dose (TID) effects are an essential concern for integrated devices that are operating in space environment. We present in this work an extensive study of TID effects in Deep-Submicron and Nanoscale CMOS technologies. Principal aspects are the changes of the transistors I-V characteristics due to TID effects, the variation of the threshold voltage and the impact of radiation on the carrier densities and mobility as well as on the electrical potentials and the leakage currents. Further, we discuss a potential solution that reduces TID effects in CMOS devices. The device level simulations consider a satellite application that orbits in Low Earth Orbit (LEO), leading to dose levels of up to 500 krad(Si). Results clearly indicate the high impact of TID on the transistor parameters, enforcing the designer to consider countermeasures in order to guarantee the circuits reliability.

Total Ionizing Dose Effects on TiN/Ti/HfO2/TiN Resistive Random-Access Memory Studied via Electrically Detected Magnetic Resonance.

We observe a gamma-irradiation induced change in electrically detected magnetic resonance (EDMR) in TiN/Ti/HfO2/TiN resistive random access memory (RRAM). EDMR measurements exclusively detect electrically active defects which are directly involved in the transport mechanisms within these devices. The EDMR response has an isotropic g-value of 2.001 ± 0.0003. The response increases dramatically with increased gamma-irradiation. We tentatively associate this EDMR response with spin dependent trap assisted tunneling (SDTAT) events at centers coupled to hafnium ions. Although our study cannot fully identify the role of these defects in electronic transport, the study does unambiguously identify changes in transport defects caused by the ionizing radiation on defects involved in electronic transport in RRAM devices. This work also contributes more broadly to the RRAM field by providing direct, though incomplete, information about atomic scale defects involved in electronic transport in leading RRAM systems.

Research on the radiation hardened SOI devices with single-step Si ion implantation

Silicon-on-insulator (SOI) devices are sensitive to the total ionizing dose effect due to the existence of buried oxide. In this paper, an extra single-step Si ion implantation into buried oxide layer prior to the normal complementary metal–oxide–semiconductor transistor (CMOS) process is used to harden the SOI wafer. The top-Si quality of the hardened SOI wafer is confirmed to be good enough for device manufacturing through various characterization methods. The radiation experiments show that the total ionizing dose tolerance of the Si implanted SOI device is improved significantly. The metastable electron traps introduced by Si implantation is also investigated by electrical stress. The results show that these traps are very instable, and electrons will tunnel into or out of the metastable electron traps quickly after hot-electron-injection or hot-hole-injection.

A Quantitative Approach to Characterize Total Ionizing Dose Effect of Periphery Device for 65 nm Flash Memory

To evaluate the total ionizing dose (TID) response of periphery devices with 65 nm flash memory, the TID effects of the main and parasitic transistor have been investigated based on the proposed novel parameter extraction approach. By analyzing post-radiation behavior of the device's drain current and interface trap density, it has been proven that the parasitic transistor demonstrates stronger radiation dependence than the main transistor. With the proposed approach, the roles of the parasitic transistor and main transistor in the TID effect are quantitatively characterized. For a W =10 μm HVN device, the main transistor Vth shows a shift of <0.1 V with a TID of 100 krad (Si), while the parasitic transistor shows shift >0.5 V with 100 krad (Si) radiation. It is concluded that the net positive charge accumulating in the shallow trench isolation oxide is responsible for the TID induced leakage and the Vth shift in the flash technology periphery device.

Radiation Hardening by the Modification of Shallow Trench Isolation Process in Partially Depleted SOI MOSFETs

Two radiation hardening processes for shallow trench isolation (STI), i.e., Si+ implantation and STI oxide nitridation are investigated, including the impact on nominal electrical characteristics and radiation hardness. The total ionizing dose effects of the nMOS devices are proved to be sensitive to the STI radiation hardening process conditions. There are optimum process conditions to achieve the best effectiveness of radiation hardening. Then, a 130-nm radiation-hardened PDSOI technology has been developed. The radiation hardness is verified by static random access memories with small storage capacities.

An Advanced SOI Pixel Sensor With Anti-Punch-Through Implantation

An advanced silicon-on-insulator (SOI) pixel sensor with an anti-punch-through structure is proposed to suppress the effect of total ionizing dose (TID) and crosstalk between the electronics and the sensor. A buried p-well (BPW) and a buried n-well (BNW) are both connected to their respective voltages to shield SOI circuits from the sensor. BNW is used as an electrode with controllable potential, which provides similar functionality as middle silicon in double SOI (DSOI). The biased BPW and anti-punch-through implant are adopted to form a potential barrier to holes in BPW. The lateral electric fields induced by the sidewalls of the pixel accelerate electrons to the N+ charge collector. 2-D and 3-D physical-level simulations are presented to compare this structure with DSOI. The simulation results show that an appropriate operating biasing voltage under a fully depleted condition can be secured by adjusting the anti-punch-through doping. The TID effects, the parasitic capacitance between the electronics and the charge collector, and the charge collection efficiency have been studied.

A Multi-Time-Step Finite Element Algorithm for 3-D Simulation of Coupled Drift-Diffusion Reaction Process in Total Ionizing Dose Effect

In order to study the total ionizing dose degradation and enhanced low dose rate sensitivity effect for semiconductor devices in the space environment, we simulate the drift-diffusion-reaction processes in a 3-dimensional SiO2–Si system. Since the time scale of the drift-diffusion processes is much larger than that of the chemical reaction processes, we use a multi-time-step algorithm to calculate the two types of processes, respectively. In this paper, partial differential equations used to describe the electrodiffusion processes are solved by a finite element method, while the chemical reactions taking place independently in every mesh node are solved as ordinary differential equations. We reproduce qualitative properties of total ionizing dose effect and compare our numerical results with experimental data and other simulation results. This paper paves a way for 3-D simulation of total ionizing dose and enhanced low dose rate sensitivity with high efficiency and robustness.