Torque Magnetoresistive Random Access Memory Research Articles

Publisher Correction: Spin-transfer torque magnetoresistive random access memory technology status and future directions

Publisher Correction: Spin-transfer torque magnetoresistive random access memory technology status and future directions

Spin-transfer torque magnetoresistive random access memory technology status and future directions

Spin-transfer torque magnetoresistive random access memory technology status and future directions

Advanced Modeling and Simulation of Multilayer Spin-Transfer Torque Magnetoresistive Random Access Memory with Interface Exchange Coupling.

In advancing the study of magnetization dynamics in STT-MRAM devices, we employ the spin drift-diffusion model to address the back-hopping effect. This issue manifests as unwanted switching either in the composite free layer or in the reference layer in synthetic antiferromagnets-a challenge that becomes more pronounced with device miniaturization. Although this miniaturization aims to enhance memory density, it inadvertently compromises data integrity. Parallel to this examination, our investigation of the interface exchange coupling within multilayer structures unveils critical insights into the efficacy and dependability of spintronic devices. We particularly scrutinize how exchange coupling, mediated by non-magnetic layers, influences the magnetic interplay between adjacent ferromagnetic layers, thereby affecting their magnetic stability and domain wall movements. This investigation is crucial for understanding the switching behavior in multi-layered structures. Our integrated methodology, which uses both charge and spin currents, demonstrates a comprehensive understanding of MRAM dynamics. It emphasizes the strategic optimization of exchange coupling to improve the performance of multi-layered spintronic devices. Such enhancements are anticipated to encourage improvements in data retention and the write/read speeds of memory devices. This research, thus, marks a significant leap forward in the refinement of high-capacity, high-performance memory technologies.

Single-nanometer CoFeB/MgO magnetic tunnel junctions with high-retention and high-speed capabilities

Making magnetic tunnel junctions (MTJs) smaller while meeting performance requirements is critical for future electronics with spin-transfer torque magnetoresistive random access memory (STT-MRAM). However, it is challenging in the conventional MTJs using a thin CoFeB free layer capped with an MgO layer because of increasing difficulties in satisfying the required data retention and switching speed at smaller scales. Here we report single-nanometer MTJs using a free layer consisting of CoFeB/MgO multilayers, where the number of CoFeB/MgO interfaces and/or the CoFeB thicknesses are engineered to tailor device performance to applications requiring high-data retention or high-speed capability. We fabricate ultra-small MTJs down to 2.0 nm and show high data retention (over 10 years) and high-speed switching at 10 ns or below in sub-5-nm MTJs. The stack design proposed here proves that ultra-small CoFeB/MgO MTJs hold the potential for high-performance and high-density STT-MRAM.

Integration of BiSb Topological Insulator and CoFeB/MgO With Perpendicular Magnetic Anisotropy Using an Oxide Interfacial Layer for Ultralow Power SOT-MRAM Cache Memory

BiSb topological insulator is attractive for the spin current source in spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) thanks to its giant charge-to-spin conversion efficiency. However, the large spin Hall angles have been reported so far only in BiSb deposited on top of Co/Pt and Co/Tb multilayers. In realistic SOT-MRAM application, it is essential to integrate BiSb to CoFeB/MgO junction with perpendicular magnetic anisotropy (PMA). Here, we report a large spin Hall angle of 2.8 in junctions of bottom BiSb and CoFeB/MgO with perpendicular magnetic anisotropy using a CrOx interfacial layer, which is suitable for use in magnetic tunnel junctions (MTJ). We demonstrated SOT magnetization switching by a small current density of 3.1 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at a pulse width of 50 μs, which is an order of magnitude smaller than that in heavy metals. Our work demonstrates the capability of integrating BiSb to CoFeB/MgO-based MTJ.

Numerical study of two-terminal SOT-MRAM

A fully three-dimensional model coupling charge, spin, magnetization, and temperature dynamics is employed to study the switching behavior of the two-terminal spin–orbit torque magnetoresistive random access memory (2T-SOT-MRAM). We demonstrated that free layer (FL) spin-transfer torque (STT) switching is strongly affected by the inclusion of the SOT. The nucleation of the FL magnetization reversal is similar to the conventional three-terminal (3T)-SOT-MRAM. In comparison to the traditional STT-MRAM, the switching times and critical switching voltages are considerably reduced. Furthermore, the full thermal simulations show the significance of the heating process and temperature modeling in MRAM devices as they demonstrate a significantly lower switching time than the one in a constant temperature model.

Accurate Torque Evaluation in Elongated Ultra-Scaled STT-MRAM Devices

Emerging spin-transfer torque magnetoresistive random access memory (STT-MRAM) is attractive for stand-alone and embedded applications. STT-MRAM is nonvolatile, operates fast, and possesses excellent endurance. STT-MRAM is compatible with CMOS technology and can be integrated during the back-end-of-line process. This makes STT-MRAM promising for automotive and IoT applications, microcontrollers, frame buffer memory, and last level cache. The core of modern STT-MRAM cells consists of a magnetic tunnel junction (MTJ), which is a sandwich of two ferromagnetic (FM) layers separated by a tunnel barrier (TB). The FM layers are referred to as reference layer (RL) and free layer (FL). The magnetization of the RL is fixed, while the magnetization of the FL can be reversed. The use of MTJs with perpendicular magnetic anisotropy (PMA) permits to obtain better scalability and lower switching currents. When the magnetization vectors of the FL and RL are parallel (P), the electrical resistance is lower than when the vectors are anti-parallel (AP), which provides a way to store binary information. Importantly, the switching between these two stable configurations is achieved by purely electrical means.To reduce the footprint and benefit from shape-induced anisotropy, an ultra-scaled MRAM cell with a composite FL made of several elongated ferromagnetic pieces, separated by multiple MgO barriers, was proposed and demonstrated [1]. In elongated FLs, shown in Fig.1a, domain walls or magnetization textures can be generated during switching. In this case, additional spin torques created by the presence of magnetization gradients inside the ferromagnetic parts must be considered. This type of torque is typically modeled by the Zhang-Li expression [2]. If the spin dephasing length correctly describes the coupled charge and spin transport through the device, the expression for bulk torque must be generalized [3].In MTJs, however, there exists another torque acting on a FL close to the interface with MgO. This torque, predicted by Slonczewski [4] and Berger [5], was utilized to flip the magnetization in traditional MTJs with a FL fabricated as a flat and thin disk. It is due to the spin-polarized current coming across the TB from the RL. Electrons tunneling from the RL become spin-polarized. When entering the FL, the spin polarized electrons interact with the magnetization via the exchange interaction. When the magnetization vectors in the RL and FL are not aligned, the spin current components normal to the FL magnetization are quickly absorbed. Due to conservation of the angular momentum, the absorption of the normal component of the spin current results in a torque acting on the FL magnetization in the opposite sense. If the current is sufficiently strong, the magnetization of the FL can be switched between the two stable P and AP configurations relative to the RL.As the Slonczewski torque is localized at the interface and Zhang-Li (ZL) torque is acting in the bulk, the two torques are usually assumed to be independent. However, this is not correct [5]. Although the spin component normal to the FL magnetization is indeed quickly absorbed, the interface-polarization induced spin current parallel to the magnetization propagates into the FL at a longer distance determined by the spin-flipping length. This length is about 10nm in typical FL materials. As the interface-polarization induced spin current hits the spin texture, it modifies the ZL torque value determined by the spin polarization in the bulk. The FL in ultra-scaled MRAM cells contains a TB on both interfaces. Here, we compare the ZL torque acting on the domain wall (Fig.1b) for the case, when the interface polarization at the second TB is lower than the spin polarization in the bulk (Fig.1c) or higher (Fig.1d). It is demonstrated that the torque acting on the domain wall can be enhanced compared to the ZL value for the case of larger interface polarization than spin polarization in the bulk. B. Jinnai, J. Igarashi, K. Watanabe et al. High-performance shape-anisotropy magnetic tunnel junctions down to 2.3 nm, in Proc. IEDM Conf., 2020, pp. 24.6.1-24.6.4, doi: 10.1109/IEDM13553.2020.9371972S. Zhang and Z. Li. Roles of nonequilibrium conduction electrons on the magnetization dynamics of ferromagnets. Phys. Rev. Lett., vol. 93, 127204, 2004 doi: 10.1103/PhysRevLett.93.127204J. C. Slonczewski. Current-driven excitation of magnetic multilayers, J. Magn.Magn. Mater., vol. 159, no. 1, pp. L1 - L7, 1996, doi: 10.1016/0304-8853(96)00062-5L. Berger. Emission of spin waves by a magnetic multilayer traversed by a current, Phys. Rev. B, vol. 54, pp. 9353-9358, 1996, doi: 10.1103/PhysRevB.54.9353S. Fiorentini, M. Bendra, J. Ender et al. Spin and charge drift-diffusion in ultra-scaled MRAM cells, Sci. Rep., vol. 12, 20958, pp.1-13, 2022, doi: 10.1038/s41598-022-25586-4 Figure 1

A Comprehensive Study of Temperature and Its Effects in SOT-MRAM Devices.

We employ a fully three-dimensional model coupling magnetization, charge, spin, and temperature dynamics to study temperature effects in spin-orbit torque (SOT) magnetoresistive random access memory (MRAM). SOTs are included by considering spin currents generated through the spin Hall effect. We scale the magnetization parameters with the temperature. Numerical experiments show several time scales for temperature dynamics. The relatively slow temperature increase, after a rapid initial temperature rise, introduces an incubation time to the switching. Such a behavior cannot be reproduced with a constant temperature model. Furthermore, the critical SOT switching voltage is significantly reduced by the increased temperature. We demonstrate this phenomenon for switching of field-free SOT-MRAM. In addition, with an external-field-assisted switching, the critical SOT voltage shows a parabolic decrease with respect to the voltage applied across the magnetic tunnel junction (MTJ) of the SOT-MRAM cell, in agreement with recent experimental data.

Energy Efficient Computing With High-Density, Field-Free STT-Assisted SOT-MRAM (SAS-MRAM)

Energy efficient computing hardware has played an instrumental role in enabling novel abundant data applications and transformative new user experiences. As we look forward, many emerging nonvolatile memory technologies have been proposed to further improve the energy efficiency of tomorrow’s computing systems. Spin–orbit torque magnetoresistive random access memory (SOT-MRAM) and its variants are one class of emerging nonvolatile memory technology, which promises static random access memory (SRAM)-like performance at a higher bit-cell density. In this article, we discuss high-density, field-free spin-transfer torque (STT)-assisted SOT-MRAM (SAS-MRAM) as an emerging nonvolatile memory technology, which could drastically improve the energy efficiency of future computing systems. Such benefits are enabled by sharing the SOT line between one or many magnetic tunnel junctions (MTJs), thereby amortizing the areal and energy costs of the SOT drive transistor across multiple bits.

Growth temperature-controlled Gilbert damping and anisotropies in PLD grown epitaxial Co2FeSi Heusler alloy thin film

The utilization of spin rather than charge as a functional aspect in the electronic devices will result in an energy-efficient, thermally stable, and fast operation. Cobalt-based Heusler alloy Co2FeSi (CFS) offers excellent possibilities due to its high curie temperature, large spin polarization, and low Gilbert damping (α). Small damping makes the alloy fascinating for spin transfer torque magnetoresistive random-access memory (STT-MRAM) devices where a low α causes a low value of switching current. The present investigation explored the effect of deposition temperature on the chemical, structural and magnetic properties of the pulsed laser deposition grown single-crystal CFS film of thickness 50 nm on a lattice-matched (001) MgO substrate. The XRD data suggest that Co site atomic ordering and overall film crystallinity improved with temperature, resulting in a minimal value of α obtained from ferromagnetic resonance (FMR) experiment in the film grown at 600°C. The azimuthal angular variation (φ) of FMR field data gives a fourfold anisotropy pattern that confirms the single-crystal CFS film epitaxially grown on the MgO substrate. Two in-plane anisotropies, namely cubic (four-fold) and uniaxial, were obtained in all the samples. This investigation is crucial in the fabrication of fast spintronics based memory and processing devices.

Impact of Voltage Polarity on Time-Dependent Dielectric Breakdown of 1-nm MgO-Based STT-MRAM With Self-Heating Correction

Time-dependent dielectric breakdown (TDDB) lifetime of ultrathin (1 nm) MgO in spin-transfer torque magnetoresistive random access memory (STT-MRAM) devices has recently been shown to be driven by factors other than voltage alone. This study focuses on the specific role of asymmetry in the current flow for different polarity pulsing modes of voltage stress on the TDDB lifetime of 1-nm MgO. Numerical analysis, based on a 3-D heat-diffusion equation and spintronic simulations, has been performed to characterize the temperature rise in the devices for precise correction of self-heating to obtain a correct interpretation of MgO TDDB. It is shown that the different lifetimes for the positive and negative modes can be attributed to different temperature increases arising from self-heating. While the positive and negative modes displayed a non-Arrhenius behavior, the bipolar mode showed an Arrhenius trend in which we observed a unique bimodal behavior of TDDB activation energy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {a}}$ </tex-math></inline-formula> ) as a function of stress voltage in the ultrathin MgO stack. We discuss the role of additional driving forces, such as current, self-heating, charge trapping, and interface strain governing the breakdown mechanism along with the voltage effect.

FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance Enhancement

Spin transfer torque (STT) magneto-resistive random access memory (MRAM)-based non-volatile logic circuits require asymmetric write current to enable high efficiency. This requires methods at the device or circuit level to meet the asymmetric current requirement of STT MRAM-based circuits. In this work, we propose a novel asymmetric fin field-effect transistor (FinFET)-based access device, along with a process flow, at a 3-nm node. The proposed device uses selective fin-trimming during the replacement metal gate (RMG) process, along with a dielectric deposition in the trimmed fin regions. This process does not require a new mask design and can be easily integrated into standard CMOS technology, and thus is very attractive with respect to previously proposed devices. With 3-D TCAD modeling, we show that up to 26% asymmetricity can be achieved with this device architecture, which meets the requirement of STT MRAM-based circuits. The proposed device offers 30% lower gate capacitance with respect to previously proposed devices.

Modeling thermal effects in STT-MRAM

We employ the stochastic Landau–Lifschitz–Gilbert (sLLG) equation to explore thermal effects on switching in the spin-transfer torque magnetoresistive random access memory (STT-MRAM). The distribution of the switching times depends on the meshes used for the discretization within the finite element method (FEM) implementation and we introduce an effective temperature scaling in the thermal field calculation to mitigate the switching time distribution dependencies on the element size. Furthermore, we investigate the switching statistics of the STT-MRAM at different temperatures and show that the switching time distribution has a lower mean value, but possesses a longer tail of long switching times for the higher operating temperatures. As a result, the STT-MRAM switching with a fixed voltage pulse duration becomes more error-prone at elevated temperatures.

Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem

Spin transfer torque magneto-resistive random-access memory (STT-MRAM) has many advantages, such as scalability, persistence, practically infinite endurance, and fast access speed, that make it a promising and emerging technology for memory. However, this technology has multiple reliability issues, such as read and write reliability, higher write power, and long write latency, etc. At elevated temperatures, these issues exacerbate further. As the temperature increases massively in the latest compute nodes, we need to study and understand the effect of temperature on STT-MRAM memory writes and reliability. In this article, we propose the temperature-aware memory controller (MC) and device architecture techniques specific to STT-MRAM technology, which can improve write reliability, retention reliability, and memory power without sacrificing the performance. Our simulation results show that the proposed techniques cumulatively improve the write bit error rate (BER) on an average by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$603\times $ </tex-math></inline-formula> , increase retention reliability by 65%, along with 27% power reduction and 5.8% improved system performance over the baseline STT-MRAM-based memory subsystem.

STT-MRAM-Based Reliable Weak PUF

In recent years, micro-nano device characteristics like ferroelectrics and resistive switching are being used to build important security primitives such as Physical Unclonable Function (PUF). The micro-nano device-based hardware security primitives, although with higher security, energy efficiency, and integration density, suffer from serious reliability issues caused by process scaling. To mitigate this issue, this paper introduces a reconfigurable weak PUF based on spin-transfer torque magnetoresistive random-access memory (STT-MRAM), which adopts the crossing switches implemented with simple demultiplexes (DEMUXs) to improve the flexibility and reliability. Moreover, two algorithms, <monospace>neighboring bit lines</monospace> and <monospace>top-<inline-formula><tex-math notation="LaTeX">$n$</tex-math><alternatives><mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="hu-ieq1-3095657.gif" xmlns:xlink="http://www.w3.org/1999/xlink"/></alternatives></inline-formula></monospace> , are proposed to enlarge the gap between two parallel reading currents, thus further enhancing the reliability of PUF responses. Experimental results demonstrate that the proposed PUF scheme achieves good uniqueness (50.64 percent), uniformity (50.02 percent), and bit-aliasing ( <inline-formula><tex-math notation="LaTeX">$\approx$</tex-math></inline-formula> 49.80%). Particularly, the proposed method significantly improves the PUF reliability, achieving low bit error rate (BER <inline-formula><tex-math notation="LaTeX">$\leq$</tex-math></inline-formula> 2.13%) within the range of -20 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C to 90 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C.

A Timing-Based Split-Path Sensing Circuit for STT-MRAM.

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (VDD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal VDD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time.

SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage

Memory security has recently come into the spotlight as attackers have stepped up their efforts to gain illicit access to sensitive data or cause denial-of-memory-service via a variety of avenues like cold boot attacks, bus snooping, and physical probing or tampering. In this paper, we propose SuperVAULT, a novel secure storage solution for protecting secret data/keys by exploiting the superparamagnetic regime of nanomagnets. Through materials and dimensional engineering of the magnetic tunnel junction (MTJ) free layer, the energy barrier of spintransfer torque magnetoresistive random access memory (STTMRAM) cells can be designed to lie in the range of the thermal energy (kBT ). Such superparamagnetic MTJ (s-MTJ) cells, with an O(10 ns) retention time, need to be refreshed frequently. In the absence of data refresh (under attack conditions), the data they hold is thermally corrupted to a random state after an arbitrary but short amount of time. We leverage this property to devise a secure memory primitive and showcase its potential against cold boot and Boolean satisfiability (SAT) attacks. Further, the overheads for s-MTJ-based STT-MRAMs is shown to be promising for on-chip implementations.

Quantitative Visualization of Thermally Enhanced Perpendicular Shape Anisotropy STT-MRAM Nanopillars.

Perpendicular shape anisotropy (PSA) offers a practical solution to downscale spin-transfer torque magnetoresistive random-access memory (STT-MRAM) beyond the sub-20 nm technology node while retaining thermal stability. However, our understanding of the thermomagnetic behavior of PSA-STT-MRAM is often indirect, relying on magnetoresistance measurements and micromagnetic modeling. Here, the magnetism of a NiFe PSA-STT-MRAM nanopillar is investigated using off-axis electron holography, providing spatially resolved magnetic information as a function of temperature. Magnetic induction maps reveal the micromagnetic configuration of the NiFe storage layer (∼60 nm high, ≤20 nm diameter), confirming the PSA induced by its 3:1 aspect ratio. In situ heating demonstrates that the PSA of the storage layer is maintained up to at least 250 °C, and direct quantitative measurements reveal a moderate decrease of magnetic induction. Hence, this study shows explicitly that PSA provides significant stability in STT-MRAM applications that require reliable performance over a range of operating temperatures.

Interface imperfection effects on spin transfer torque switching: an atomistic approach

The further commercialization of spintronic memory devices depends on the development of methods by which to assess performance. This paper presents an approach to the atomistic investigation of switching performance in spin transfer torque magneto-resistive random access memory (MRAM) devices with the use of interface imperfection model. Switching simulation in the nanosecond regime was made possible under this model, and we first time demonstrate that switching time is inversely proportional to interface imperfection (i.e. roughness). In investigating the damping of CoFeB/MgO films, we analyzed the effective damping constant α eff, which cannot be accurately predicted for ferromagnetic layers of less than 2 nm using existing micromagnetic models. The proposed model includes a roughness parameter, which has nearly no effect on the effective damping constant in films of >2 nm, but a profound effect in films of <2 nm, reaching a 27% decrease in a 1.0 nm CoFeB film. Our finding is supported by the experimental data of classic references. We expect that these results will prove valuable in magnetic simulation and research on MRAM with ultrathin films.

Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits

Nonvolatile large-scale integrated circuits (NV-LSIs) with a power-gating (PG) technique can drastically reduce the wasted static power consumption, which is an attractive feature in Internet-of-Things edge devices. However, the issues of inrush current and voltage fluctuation due to PG-state transitions are preventing their advancement. This paper describes a technique for stabilizing the operation of NV-LSIs during PG by minimizing inrush current effects and voltage fluctuations. In the proposed technique, several PG switch configurations are prepared and one of them are dynamically selected in accordance with the expected operation conditions, which could minimize inrush current and voltage fluctuations in the power supply. This technique is applied to sub-array-level PG of a spin-transfer torque magneto-resistive random-access memory (STT-MRAM). As a result, inrush current level and the recovery time of the power supply from a sleep state are reduced by up to 83.8% and 68.7%, respectively, while satisfying given performance requirements.