Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits

Abstract

Nonvolatile large-scale integrated circuits (NV-LSIs) with a power-gating (PG) technique can drastically reduce the wasted static power consumption, which is an attractive feature in Internet-of-Things edge devices. However, the issues of inrush current and voltage fluctuation due to PG-state transitions are preventing their advancement. This paper describes a technique for stabilizing the operation of NV-LSIs during PG by minimizing inrush current effects and voltage fluctuations. In the proposed technique, several PG switch configurations are prepared and one of them are dynamically selected in accordance with the expected operation conditions, which could minimize inrush current and voltage fluctuations in the power supply. This technique is applied to sub-array-level PG of a spin-transfer torque magneto-resistive random-access memory (STT-MRAM). As a result, inrush current level and the recovery time of the power supply from a sleep state are reduced by up to 83.8% and 68.7%, respectively, while satisfying given performance requirements.