Multilevel Inverter Topology Research Articles

Enhancing power conversion efficiency in five-level multilevel inverters using reduced switch topology

This paper presents extensive research on improving the power conversion efficiency of five-level multilevel inverters (MLIs) by utilizing a reduced switch topology. MLIs have received an abundance of focus because of their ability to generate high-quality output waveforms and have better harmonic outcomes than traditional two-level inverters. The high number of switches in MLIs, on the other hand, can result in increased power losses and lower overall efficiency. In this paper, a novel reduced switch topology for five-level MLIs, which is having five switches is proposed with the aim of minimizing power losses while preserving superior performance due to lesser number of switches. To achieve efficient power conversion, the proposed topology employs advanced pulse width modulation control strategies and optimized switching patterns. The simulation results show that the minimized switch topology improves the power conversion efficiency of the five-level MLI, resulting in lower losses and better overall system performance. The total harmonic distortion (THD) value of the output current has been reduced to 7.12% and the efficiency has been achieved to 96.92%. The findings of this investigation help to advance MLI technology, allowing for more efficient and reliable power conversion in a variety of applications such as renewable energy systems, electric vehicles, and industrial drives.

Performance evaluation of novel 9-level RSMLI topology for grid-tied solar-PV system

The shortage of traditional fossil fuels like coal, petrol and natural-gas are increased day-by-day, fulfills the most of energy demand. Most of engineers are trying to maximize the energy demand by employing renewable energy with existing micro-grid system. Owing to merits, the solar-PV system plays a significant alternative among all other renewable energy sources due to abundant and virtuous nature. For grid-tied solar-PV system, the cascaded H-bridge multilevel inverter is the most significant over the classical 2-level inverter due to provision of isolated input DC sources. But the cascaded H-bridge topology is designed for limited voltage levels due to its larger number of switches for higher voltage levels, high cost, large-size, and more weight. To alleviate these demerits, a reduced-switch multilevel inverter has been generally preferable for higher voltage levels. In this work, a novel 9-level reduced-switch multilevel inverter (RSMLI) topology has been proposed by utilizing low number of switching devices. The performance of proposed novel 9-level RSMLI topology has been verified in grid-tied solar-PV system by using MATLAB/Simulink tool, simulation results are presented with attractive comparisons.

Performance analysis for induction motor fed by reduced switch symmetrical multilevel inverter topology

Due to its capacity to supply more voltage levels than conventional 2-level inverters, multilevel inverters have attracted a lot of attention in recent years. Multilevel inverters may produce output waveforms that nearly approximate sinusoidal waveforms because to this characteristic, which also significantly lowers harmonic distortion. In many different power conversion systems, the introduction of reduced switch symmetrical multilevel inverter topologies has drawn significant interest. Numerous benefits, such as higher output voltage quality, reduced harmonic distortions, and increased power conversion efficiency, are provided by these novel topologies. The inclusion of these inverters in the feeding of induction motors is one of their many prominent uses. In this paper, a generalized topology is presented that generates nine levels using nine switching devices. To reduce complexity, switching pulses are generated using a low frequency pulse width modulation technique. MATLAB/Simulink is used to analyze the performance assessment of a unique three-phase symmetric cascaded multilevel inverter-based reduced switch symmetrical inverter fed induction motor drive, brushless DC (BLDC) motor and grid has been verified. According to the findings the total harmonic distortion (THD) is found to be 15% for a three-phase system and as the number of levels increases to 17 level the THD is 7.10%.

SHE PWM based 21 level inverters with hardware analysis

Recently, the advancement of multilevel inverters (MLI) has been a crucial factor in high power and medium voltage applications. This MLI has multiple topologies and has been used in a variety of applications. Cascaded MLI is preferred over other forms of multilevel inverter topologies. Nonetheless, significant obstacles are encountered when implementing these topologies. They necessitate an increased number of switches, DC sources, capacitors, and diodes. Increased losses and total harmonic distortion (THD) will be present in the system. In addition, the MLI is more expensive. The better construction of a multilevel inverter results in more output levels with fewer switches, sources, and driver circuits, as well as low THD. A new single-phase cascaded asymmetrical DC voltage sources based multilevel inverter design and the selective harmonic elimination (SHE) approach are used to attain these goals. After confirming in MATLAB/Simulink, the hardware implementation of the multilevel inverter in 21 levels was completed in this article.

Sensorless speed controller of an induction motor with MRAS-based model predictive control

Speed sensors play critical role in induction motor (IM) control systems. However, the use of these sensors cause several drawbacks such as increasing the overall cost, decreased reliability on control and increased noise problems in data acquisition. The sensorless control methods also have been proposed in control systems of IM to increase the overall performance. On the other hand, model predictive controllers (MPCs) which is one of the most recently used controller methods require the speed measurement to perform speed and torque control of an IM. In addition to control method, the topology of voltage source inverter (VSI) affects the overall efficiency of the IM drive because of its losses and total harmonic distortion (THD) ratios delivered by the topology. The main proposal of this study is to implement an IM drive built with a three-level active neutral point clamped (3L-ANPC) voltage source inverter (VSI) and to propose an MPC that eliminates sensor requirement in speed control of IM. The proposed IM drive takes benefits of multilevel inverter topology, which reduces the torque ripple, enables low switching frequency and provides decreased harmonic distortion. The switching pulses of ANPC VSI are generated by the proposed sensorless MPC method for controlling the torque of IM. The modelling and experimental verification of the ANPC based IM drive have been carried out and the sensorless MPC controller has been validated in this study. There two types of model reference adaptive system (MRAS) have been proposed to ensure precise estimation of IM speed that should be supplied to MPC controller. These MRAS methods are titled as the rotor flux based model reference adaptive system (MRASF), and the stator current based model reference adaptive system (MRASCC) according to estimation references. The proposed MPC-based IM drive has been analyzed under variable speed and torque circumstances to detect the efficiency and reliability of MRASF and MRASCC algorithms. The efficiency indicators such as flux and torque responses, and speed control of the suggested MPC IM drive are validated with experimental analysis. The results of revealed that the IM effectively tracks the reference speed and produces the required torque depending to the precise control of proposed MPC algorithm.

Modulated model predictive current control technique for triple‐boost seven‐level switched capacitor‐based inverter topology

SummaryTraditionally, the finite control set‐based model predictive current control technique (MPC2T) inherently wrenches from the variable switching frequency of operation. To obtain the fixed switching frequency of operation, different types of predictive control approaches have been reported in the literature. However, these are complex while going to single‐phase higher‐level inverter topologies and are not to be generalized in a simple manner. In this paper, a new generalized modulated MPC2T has been proposed for single‐phase switched capacitor‐based multilevel inverter (SC‐MLI) topologies. In this technique, the optimum inverter output voltage (O‐IOV) has been generated by nullifying the derivative of the cost function. The normalized O‐IOV is fed to a new single modulating floor function (F2) single carrier‐based pulse width modulation technique. Compared to all routine PWM approaches, this specific F2‐based modulation stage is extremely straightforward even for higher‐level inverter topologies. The sensorless voltage balancing of switched capacitor topologies completely eradicates the need for weighting factors in predictive algorithms. To verify the robustness and performance of the perspicuous proposed technique, the conventional triple boost SC‐MLI topology has been considered and elucidated with the different steady and dynamic operation of results.

A New Symmetrical Source-Based DC/AC Converter with Experimental Verification

This research paper introduces a new topology for multilevel inverters, emphasizing the reduction of harmonic distortion and the optimization of the component count. The complexity of an inverter is determined by the number of power switches, which is significantly reduced in the presented topology, as fewer switches require fewer driver circuits. In this proposed topology, a new single-phase generalized multilevel inverter is analyzed with an equal magnitude of voltage supply. A 9-level, 11-level, or 13-level symmetrical inverter with RL load is analyzed in MATLAB/Simulink 2019b and then experimentally validated using the dSPACE-1103 controller. The experimental verification of the load voltage and current with different modulation indices is also presented. The analysis of the proposed topology concludes that the total required number of components is lower than that necessary for the classical inverter topologies, as well as for some new proposed multilevel inverters that are also compared with the proposed topology in terms of gate driver circuits, power switches, and DC sources, which thereby enhances the goodness of the proposed topology. Thus, a comparison of this inverter with the other topologies validates its acceptance.

Review of Multilevel Level Inverter Using Different Topologies

This paper provides a concise overview of various multilevel inverter (mli) topologies. The conventional two-level voltage source inverter (vsi) necessitates a filter to generate sinusoidal output waveforms, which can be challenging at high frequencies due to switching losses. To address this issue, multilevel inverters offer lower switching frequencies and reduced total harmonic distortion (thd), eliminating the need for filters and large transformers. Moreover, a few advantages of mli inverters are reduced switching losses, better performance at high switching frequencies, and higher power quality (almost pure sinusoidal). Nevertheless, adding to the complexity of the system is the requirement for each switch to have its own gate driver in order to perform mli. Thus, it's imperative to decrease the mli's number of switches. In order to reduce the number of switches needed, this paper reviews some of the various current topologies. Applications such as voltage regulation, var compensation, harmonic filtering in power systems, and user interface for renewable energy have led to the development of cascaded h-bridge multilevel inverters. For solar applications, a modified cascaded h-bridge multilevel inverter (mli) is used. Cascaded h-bridge topology multilevel inverter will aid in reducing the number of switches. Comparing this concept to other multilevel inverters, the switching complexity is reduced.

A new single modulating and single carrier signal based control technique for symmetrical and asymmetrical multilevel inverter topology

Abstract In literature, to generate gate pulses for any inverter topology, most of the authors are using a single modulating signal with (level-1) or (level-1)/2 carrier-based pulse width modulation (PWM) techniques and single carrier (SC) signal with (level-1)/2 modulating signal based PWM techniques. Then, while going to higher-level inverter topologies, the complexity of the PWM control approach in both cases can increase. To reduce the control complexity, few authors have reported a single modulating signal with single carrier-based PWM techniques. However, these techniques need more mathematical equations and if-else loops. This article proposes a new single-modulating and single-carrier signal-based generalized PWM control approach using floor function (FF). This technique has been verified by considering one of the single-phase conventional symmetrical and asymmetrical multilevel inverter (MLI) topologies. Generally, FF rounds the value to the nearest integer towards the negative infinity. The proposed PWM control implementation process is very simple and suitable for both high switching frequency (HSF) and low switching frequency (LSF) operations. The proposed control technique (PCT) has been experimentally verified with different steady-state and transient-state studies of results under standalone operation.

Performance Analysis of a Novel Multilevel Inverter with Reduced Number of Switches

Multilevel inverters (MLI) are important and widely accepted under DC to AC converter family for medium and low power applications. In the paper a “new inverter topology” for multi-level is developed. The primary purpose of the work is to reduce the switch count number for considerable level of output voltage and also to reduce gate drives required. It also aims at analysis of performance of proposed topology of new multilevel inverter. Output of fifteen stages is generated from the proposed topology. For which only eight switching devices, four diode and three asymmetrical sources are used. Thus, the space and cost for installation is reduced. The designed topology is simulated with normal “pulse width modulation (PWM)” as well as “sinusoidal pulse width modulation (SPWM)”. Both the Simulation results are discussed with respect to “output voltage, current, Total Harmonic Distortion (THD)”. A comparative study is also made between the topology developed with few other latest MLI topologies. DOI: https://doi.org/10.52783/pst.236

Moth flame algorithm-based optimization of a reduced switch multilevel inverter topology suitable for standalone application

Moth flame algorithm-based optimization of a reduced switch multilevel inverter topology suitable for standalone application

Comparing performance and complexity of TCHB and CHB multilevel inverters using NLC technique

This paper presents a modulation strategy applied to a 13-level three-phase transistor clamped H-bridge (TCHB) inverter, aimed at a renewable and electric vehicle drives application. A comparison is performed between the TCHB inverter and a traditional cascaded H-bridge (CHB) inverter, considering circuit complexity, switching losses, and total harmonic distortion (THD) attained from each multilevel inverter topologies. The TCHB inverter achieves a 13-level output with only 15 switches, whereas the conventional CHB inverter requires 24 switches. The modulation technique, employing a nearest level control, yields improved output quality for both the TCHB and CHB multilevel inverters. The results demonstrate that this strategy effectively minimizes the overall THD. Notably, previous modulation techniques mainly focused on carrier-based PWM or SVPWM, making this approach distinctive. The FFT analysis reveals a voltage THD of 5.49% for TCHB and 5.15% for CHB, indicating a marginal difference in THD content for each multilevel inverter. Despite the CHB inverter experiencing double the switching stress compared to TCHB, since less switches are required in the TCHB inverter, consequently, the system's total cost and complexity are reduced. The achieved results are verified through the use of simulations carried out in the MATLAB Simulink.

2DOF‐FOPID‐IF control with improved sparrow modulation for cascaded H‐bridge multilevel inverter in PV applications

SummaryPhotovoltaic (PV) systems benefit from the cascaded H‐bridge multilevel inverter (CHMLI) topology due to its high flexibility and efficiency. However, PV mismatches in three‐phase grid‐connected systems result in an unbalanced power supply, which leads to an unbalanced grid current. Proportional integral derivative (PID) controllers can be used to control H‐bridge inverters because of their simplicity of tuning as well as their basic structure. However, due to the nonlinearity and high sensitivity of the PID controller, its performance declines as a result of high overshoot, high settling time, and high rise time during significant external disturbances. Moreover, the switching angle of the inverter must be adjusted to provide the required fundamental voltage while reducing harmonic content. In order to address this problem, a control technique with modulation compensation is proposed. The present work offers a two‐degree‐of‐freedom fractional‐order PID controller with an integrated filter (2DOF–FOPID–IF). Moreover, the optimum switching angles are determined for the CHMLI by employing an improved sparrow optimization (ISO) algorithm. To prove the practicality of the suggested technique, simulation, and experimental data are compared with the existing techniques. The proposed technique shows better performance in terms of settling time, overshoot, rise time, and low harmonics.

Cascaded H–Bridge Multilevel Inverter: Review of Topologies and Pulse Width Modulation

Multilevel inverters (MLIs) have become more popular for medium-voltage and high-power applications. The cascaded H-bridge multilevel inverter (CHBMLI) is one of the three most popular topologies of MLIs. It was more reliable due to its fewer components per level. The number of possible output voltage levels is more than twice the number of DC sources, the most suitable topology for integration with renewable energy sources, easy to design, and has good performance with modularity. The main disadvantage of CHBMLI is the need for separate DC sources for each H-bridge. However, this can be considered as an advantage to be employed in renewable energy applications. This paper provides a review of CHBMLI topologies and pulse width modulation (PWM) techniques, including fundamental and high switching frequency techniques, such as selective harmonic elimination (SHE), space vector modulation (SVM), nearest level modulation (NLM), and Carrier-Based PWM.

A new submodule‐based generalized multilevel inverter topology with reduced switches and DC sources

SummaryMultilevel inverters are known as essential converters in renewable sources. First, in this paper, a new submodule is presented, and based on it, a new sub‐multilevel inverter is presented. The proposed sub‐multilevel inverter consists of several unidirectional and bidirectional switches and DC voltage sources. Then, the generalized topology, developed in two modular and cascaded modes, is presented to increase production levels. The proposed submodules are connected in series in the modular topology, increasing production levels. The proposed topology to produce the maximum output levels has the minimum number of IGBTs, drivers, DC voltage sources, etc. Mathematical analyses for conduction and switching losses are provided, and mathematical analyses for the number of devices and voltage across the switches are also presented. In addition to the mathematical analysis of losses, the simulation results are also presented. A general comparison of proposed topology components is presented to demonstrate their advantages. This comparison shows that the proposed topology has the minimum number of power electronic devices. In this paper, nearest level modulation is used to control the proposed topology. The simulation and experimental results of the proposed sub‐multilevel verify the performance of the proposed topology.

Comparative study of single-phase multilevel cascaded transformerless inverters with different modulation methods

This paper presents an in-depth exploration of a single-phase multilevel cascaded H5 (CH5) transformerless inverter employing both phase-shifted PWM (PS-PWM) and level-shifted PWM (LS-PWM) methodologies. A comparative analysis is conducted with the conventional multilevel inverter (MLI) topologies, specifically the cascaded H-bridge (CHB) and H5 inverter configurations. The investigation delves into the impact of modulation index variations, load fluctuations, and modulation methods on the inverter's operational performance.While switches in the CHB-MLI operate continuously at the carrier frequency state using PS-PWM and LS-PWM methods, the CH5-MLI exhibits a unique behavior with some switches toggling at high frequency, while others synchronize with the grid frequency. The CH5-MLI topology demonstrates efficiency improvements and a reduction in total harmonic distortion (THD). Notably, employing the LS-PWM method yields more significant efficiency enhancements and THD reduction compared to the PS-PWM method. To analyze power loss characteristics under diverse operating conditions, the PLECS simulation environment is leveraged for calculating conduction and switching losses.The application of phase-shifted and level-shifted carrier-based pulse width modulation strategies to high and low-frequency switching switches results in minimized output harmonics, elevated operator safety, and enhanced overall reliability and efficiency. This work contributes significantly to the field by offering a detailed exploration of the CH5-MLI topology's dynamic behavior, modulation strategies, and their collective impact on performance metrics such as efficiency, THD, and power losses.

Fault-Tolerant Analysis of 5-level Modified T-type and Packed U Cell MLI

ABSTRACT In this work, 5-level modified T-type and modified Packed-U-Cell (PUC) multilevel inverter (MLI) topologies are designed with reduced device count for the reliability analysis of the MLI under faulty conditions. This work aims to incorporate the fault either by loss of an individual switch or due to the loss of a single h-bridge leg. Also, the proposed T-type and PUC inverter have an inherent self-voltage balancing capability that reduces the complexity and enhances the circuit’s reliability. First, the proposed topologies are simulated using Matlab/Simulink environment, and the results obtained are then compared with the conventional MLI. Finally, both MLIs are experimentally tested on a laboratory prototype as a proof of concept to validate the analytical developments.

A novel 7-level reduced-switch MLI topology fed PMSM drive for electric vehicle system

The compact and efficient design motivates the renewable energy-powered permanent magnet synchronous motor drive for electric vehicle applications. The available renewable energy is interfaced with a power drive by employing an electronic commutator such as a conventional 3-level inverter. But, the multilevel inverter produces favorable merits by producing staircase output voltage from several input direct current (DC) sources. The cascaded H-bridge multilevel inverter plays a significant role in many applications, but it was developed only for limited voltage levels. The major problem in cascaded h-bridge multilevel inverter (CHBMLI) requires more switching devices for higher voltage levels, which increases the size, cost and space of the electric vehicle (EV). To overcome above-mentioned problems, a new objective has been developed by employing the novel Reduced-switch multilevel inverter topology for higher voltage levels. This improves the voltage quality and reducing the harmonic level, and common-mode voltage issues. The main contribution of this work is, developing the novel 5-level, 7-level reduced-switch multilevel inverter (RSMLI) topologies with reduced switching devices with favourable merits over CHBMLI topology. Finally, the performance of proposed novel 5-level and 7-level RSMLI topologies fed PMSM drive for EV system has been verified, by using MATLAB/Simulink computing tool, and simulation results are presented with comparisons.

Comparative Study of THD Characteristics in Different Cascaded H-Bridge Configurations for Multilevel Multicarrier Modulation

This paper presents a comprehensive comparative study investigating the Total Harmonic Distortion (THD) characteristics of various Cascaded H-Bridge (CHB) configurations utilized in Multilevel Multicarrier Modulation (MMCM) systems. The research examines different CHB topologies, focusing on their impact on THD performance in MMCM applications. Through theoretical analysis and simulation, this study evaluates THD levels under varying operating conditions, including different modulation schemes and switching strategies. A discussion on main topologies of multilevel inverter namely H-bridge, NCP(neutral point clamped),NCP- H and flying capacitor is carried out utilizing carrier based PWM methods. Comparison is done on basis of harmonic component, THD and nu of component used by 3, 5 and7 level cascaded H-bridge topology respectively. To support the result a detailed study is carried out using MATLAB Simulink software. Keywords- Multilevel inverter, PWM, THD, NCP, NCP-H.

Design and Implementation of Multilevel Inverter Topology with Reduced Switching Components

Multilevel inverters play a vital role in renewable energy applications. In this paper we designed a new MLI topology for various renewable energy sources application with fewer switches using the multiple pulse width modulation technique. H-Bridge MLI topology is designed and implemented in an asymmetrical configuration. The equal amplitude of DC sources is symmetric, and unequal amplitude DC sources are used asymmetrically. On operating the MLI in an asymmetric design with four voltage sources, eight switches and 15-level output is produced, while in symmetric mode 9-level output is produced. The low-frequency modulation scheme is applied with a designed switching pattern where the switching period is pre-determined. The proposed topology is designed with reduced switches, minimal total harmonic distortion (THD) and the results are compared with conventional multilevel inverter topologies. The proposed MLI topology performance is validated and verified with number of switches and voltage levels and mainly LSR & CLF. Fifteen-level MLI operation is also simulated using MATLAB platform for experimental validation. The results produced by proposed topology are found to be encouraging and superior than any other conventional topology.