Top Silicon Layer Research Articles

Transmission Electron Microscopy Study of Stacking Fault Pyramids Formed in Multiple Oxygen Implanted Silicon-on-Insulator Material

The microstructure of various shapes of stacking fault pyramids (SFPs) formed in multiple implant/anneal Separation by Implanted Oxygen (SIMOX) material were investigated by plan-view and cross-sectional transmission electron microscopy. In the multiple implant/anneal SIMOX, the defects in the top silicon layer are confined at the interface of the buried oxide layer at a density of <TEX>${\sim}10^6\;cm^{-2}$</TEX>. The dominant defects are perfect and imperfect SFPs. The perfect SFPs were formed by the expansion and interaction of four dissociated dislocations on the {111} pyramidal planes. The imperfect SFPs show various shapes of SFPs, including I-, L-, and Y-shapes. The shape of imperfect SFPs may depend on the number of dissociated dislocations bounded to the top of the pyramid and the interaction of Shockley partial dislocations at each edge of {111} pyramidal planes.

Design guideline of a thin film SOI power MOSFET for high thermal stability

This paper proposes the design guidelines of the thin-film reduced surface field (RESURF) SOI power MOSFET for high thermal stability based on experimental and simulation results. The results show that the thinner top silicon layer is preferable, which realize the lower leakage current and smaller degradation of the on-resistance. In higher temperature operation, it is important to suppress the parasitic bipolar effect to prevent the reduction of the breakdown voltage.

Nano silicon top-layer for composite-induced multiphasic enhancement of thermal stability of hardness of diamond-like carbon nanofilm at 900 °C

The effect of 25-nm silicon top-layer on the hardness and thermal stability of 100-nm diamond-like carbon (DLC) film annealed at 750–900°C has been investigated. The evolution of surface morphology, microstructure and reaction between C and Si was examined by high resolution scanning/transmission electron microscope, Raman and FTIR spectroscopy. The hardness of films was investigated using nano-indentation. After 750–900°C annealing, the hardness of single carbon layer greatly decreased at 750°C and then slightly increased at 900°C due to the formation of SiC at the interface between the single C film and the Si substrate. In contrast, no significant variation occurred on the hardness of two-layer Si/C film under RTA at 750–900°C. Although the higher annealing temperature resulted in higher sp2/sp3 bonding ratio as well as more sp2 bonding formation in the carbon layer to soften the structure, the added Si top-layer can protect DLC from reaction with environmental oxygen and sustain the hardness of the composite film because of the multiphasic formation with extra SiC on the surface and at the interface between the C layer and Si substrate through great interdiffusion between Si and C for extending DLC high-temperature application.

Quantitative Analysis of Surface Morphology of Boron-Doped Zinc Oxide for Microcrystalline Silicon Solar Cells

The optimization of textured boron-doped conductive zinc oxide (ZnO:B) films deposited by metal organic chemical vapor deposition (MOCVD) for hydrogenated microcrystalline silicon (µc-Si:H) solar cells was performed. We found that the argon (Ar) plasma treatment of a textured ZnO:B substrate is effective in improving the open-circuit voltage and fill factor of µc-Si:H solar cells. We proposed (tan θ)/λ2 as an evaluation factor and found that there is a clear correlation between the (tan θ)/λ2 of textured ZnO:B films and the open-circuit voltage of µc-Si:H solar cells. Moreover, the effect of the surface morphology of a textured ZnO:B substrate on the growth of intrinsic hydrogenated amorphous silicon (i-a-Si:H) top layers was examined to obtain the optimum conditions for preparing a-Si:H/µc-Si:H tandem solar cells. We confirmed that our proposed evaluation factor (tan θ)/λ2 could be used to obtain the surface morphology of i-a-Si:H top layers that are appropriate for µc-Si:H bottom-cell deposition.

High-temperature piezoresistive pressure sensor based on implantation of oxygen into silicon wafer

Silicon on insulator (SOI) substrates can be prepared using ion implantation of oxygen. For piezoresistive detection, the top layer (0.2μm thickness) of silicon is used as the active material due to its excellent monocrystalline properties. The piezoresistive effect of the top silicon layer of the SOI wafer is analyzed using a cantilever structure. Results show that under certain doping concentration conditions, the longitudinal piezoresistive coefficients of 〈110〉 crystal direction silicon decrease with temperature, while transverse piezoresistive coefficients are less affected by temperature. At 300°C, Si 〈110〉 crystal direction has larger longitudinal and transverse piezoresistive coefficients, which make it suitable for high temperature piezoresistive pressure sensor production. The pressure sensor chip structure is simulated and analyzed using the finite element method. The pressure gauge chips are manufactured using MEMS techniques. The manufactured sensors are measured with an applied pressure from 0 to 6.0MPa at 300°C. The test results show that the sensitivity is approximately 30mV/(mAMPa), the non-linearity is less than 1.5‰FS, and the repeatability is less than 0.3‰FS. This research shows that the SOI piezoresistive pressure sensor could reliably work at high temperatures up to 300°C.

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n+-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (EI), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 μm), the EI and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.

High efficiency a-Si:H/a-Si:H solar cell with a tunnel recombination junction and a n-type μc-Si:H layer

In this paper, a-Si:H/a-Si:H tandem solar cells have been fabricated using a plasma enhanced chemical vapor deposition. The solar cell has a structure of glass/textured-SnO2/p-a-SiC:H/i-a-Si:H/n-μc-Si:H/p-μc-Si:H/p-a-SiC:H/i-a-Si:H/n-μc-Si:H/gallium-doped zinc oxide/Ag. Higher efficiency in a-Si:H/a-Si:H tandem solar cells can be achieved by use of a good tunnel recombination junction (TRJ) and current matching. Accordingly, solar cells with a n-μc-Si:H/p-μc-Si:H TRJ are investigated. This paper studies the influence of the thickness of the top intrinsic amorphous silicon (i-a-Si:H) layer with regard to short circuit current density and current matching between the top and the bottom cells. Experimental results with lab-fabricated samples show that the optimal thickness of the i-a-Si:H layer in the top and bottom cells is 60 and 250nm, respectively. An initial conversion efficiency of 10.29% is achieved for the optimized a-Si:H/a-Si:H tandem solar cell. Light-induced degradation of the solar cells is about 17%.

Design of a 1200-V Thin-Silicon-Layer p-Channel SOI LDMOS Device

A 1200-V thin-silicon-layer p-channel silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor is designed. The device named INI SOI p-LDMOS is characterized by a series of equidistant high concentration n+ islands inserted at the interface of a top silicon layer and a buried oxide layer. Accumulation-mode holes, caused by the electric potential dispersion between the device surface and the substrate, are located in the spacing between two neighboring n+ islands, and greatly enhance the electric field of the buried oxide layer and therefore, effectively increase the device breakdown voltage. Based on a 2-μm-thick buried oxide layer and a 1.5-μm-thick top silicon layer, a breakdown voltage of 1224 V is obtained, resulting in the high electric field (608 V/μm) of the buried oxide layer.

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n+-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n+-regions effectively enhance the electric field of the buried oxide layer (EI) and reduce the electric field of the silicon layer (ES), resulting in a high breakdown voltage (VB). It is shown by the simulations that the enhanced field ΔEI and reduced field ΔES by the accumulated holes reach to 449V/μm and 24V/μm, respectively, which makes VB of ICI PSOI increase to 663V from 266V of the conventional PSOI on 5μm silicon layer and 1μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1mW/μm.

Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Silicon-on-diamond (SOD) wafers potentially present thermal advantages over standard silicon-on-insulator (SOI) counterparts based on SiO2 as the buried insulating layer. This work reports the fabrication of high quality SOD wafers by the bond and etch back SOI process. One key parameter in the CVD diamond growth process is the substrate temperature. We focused here on two processes based on either high or low processing temperature to produce nanocrystalline diamond (NCD) on silicon. Both type of NCD films have been analyzed via Raman spectroscopy. Results have been correlated with scanning electron microscopy observations. In a second part, SOD wafers are fabricated and the crystalline quality of the active silicon layer is assessed via Raman measurements and high resolution transmission electron microscopy imaging. It is shown that the growth of diamond did not induce any structural defect or strain in the thin top silicon layer. Eventually, we demonstrate the efficiency of diamond integration thanks to micro-Raman spectroscopy, where the probing laser simultaneously generates Raman signal and controlled local heating. Our SOD wafers evidence a thermal resistance reduction of about 70% compared to conventional SOI materials, with heat source spatial extension in the micron range.

Silicon nanoparticle synthesis by short-period thermal anneals at atmospheric pressure in argon

Silicon nanoparticles have been studied for a wide variety of applications including nanoelectronic, photovoltaic, and optoelectronic devices. In this work, silicon nanoparticles were synthesized by short-period annealing of silicon-on-insulator substrates to temperatures ranging between 600 and 900 °C in argon gas at atmospheric pressure. Two different top silicon layers were deposited by ion-beam sputtering onto oxidized substrates. The thinner 6 nm top layer samples were annealed to temperatures for 30 s periods while thicker 15 nm top layer samples were annealed for 60 s periods. For both sets of samples, nanoparticles were observed to form at all the anneal temperatures through imaging by AFM. One long-period UHV anneal study, with 30-min anneal times, observed nanoparticle formation at temperatures similar to the current work while another similar long-period UHV anneal reported nanoparticle formation only above well-defined formation temperatures that depended upon the starting top layer thickness. In the current work, the average nanoparticle radius was found to increase both with the final anneal temperature and anneal period. For the highest anneal temperatures of the 6 nm top layer samples, a changing surface topography indicated that the thinner Si source layer was becoming depleted and the nanoparticle formation process was nearing completion. No such changes were observed for the thicker 15 nm samples at the same temperatures.

A novel analytical model of the vertical breakdown voltage on impurity concentration in top silicon layer for SOI high voltage devices

A novel analytical model of the vertical breakdown voltage (VB , V ) on impurity concentration (Nd ) in top silicon layer for silicon on insulator high voltage devices is first presented in this article. Based on an effective ionisation rate considering the multiplication of threshold energy εT in the electron, a new formula of silicon critical electric field ES , C on Nd is derived by solving a 2D Poisson equation, which increases with the increase in Nd especially at higher impurity concentration, and reaches up to 68.8 V/µm with Nd = 1 × 1017 cm−3 and 157.2 V/µm with Nd = 1 × 1018 cm−3 from the conventional about 30 V/µm, respectively. A new physical concept of critical energy εB is introduced to explain the mechanism of variable high ES , C with heavy impurity concentration. From the ES , C , the expression of VB , V is obtained, which is improved with the increasing Nd due to the enhanced ES , C. VB , V with a dielectric buried layer thickness (tI ) of 2 µm increases from 428 V of 1 × 1017 cm−3 to 951 V of 1 × 1018 cm−3. The dependence of Nd and top silicon layer thickness (tS ) for an optimised device is discussed. 2D simulations and some experimental results are in good agreement with the analytical results.

Microcantilever deflection compensation with focused ion beam exposure

We report a silicon microcantilever deflection compensation technique using a focused ion beam (FIB). We find that microcantilevers fabricated in the top silicon layer of a silicon-on-insulator wafer often have a residual deflection up out of the plane of the silicon, after release by hydrofluoric (HF) acid in which the underlying silicon dioxide is removed. We investigate compensating the out-of-plane deflection with a dose of Ga ions in the anchoring region of each microcantilever. Using this technique, deflection compensation is performed on an array of twenty-two 300 µm long and 0.65 µm thick microcantilevers. The average deflection is reduced from 919 nm ± 232 nm after HF release to –9 nm ± 34 nm after FIB compensation.

Influence of the adatom diffusion on selective growth of GaN nanowire regular arrays

Molecular beam epitaxy (MBE) on patterned Si/AlN/Si(111) substrates was used to obtain regular arrays of uniform-size GaN nanowires (NWs). The silicon top layer has been patterned with e-beam lithography, resulting in uniform arrays of holes with different diameters (dh) and periods (P). While the NW length is almost insensitive to the array parameters, the diameter increases significantly with dh and P till it saturates at P values higher than 800 nm. A diffusion induced model was used to explain the experimental results with an effective diffusion length of the adatoms on the Si, estimated to be about 400 nm.

Silicon overgrowth atop low-dimensional Mg2Si on Si(111): structure, optical and thermoelectrical properties

The growth of silicon cap layers atop Mg2Si nanocrystallites (NCs) and Mg2Si two-dimensional layer with structure (2/3√3×2/3√3)-R30° were studied by methods of AES, EELS, AFM, optical and Raman spectroscopy. It was established that method of solid phase epitaxy (SPE) ensures the embedding of Mg2Si NCs in polycrystalline quality silicon cap layer at temperatures not higher than 920 K. The increase of the temperature higher than 970 K results to the moving of silicide NCs toward the surface between silicon grains in cap layer, following their destruction and Mg desorption from the surface. The MBE method with temperatures 430–485 K was used to the embedding of continuous 2D Mg2Si layer with structure (2/3√3×2/3√3)-R30° in silicon top layer (9–20 nm) with monocrystalline grains. Investigations of thermoelectrical properties of grown nanoheterostructures have shown that a Seebeck coefficient (α∼130μV/K) increases in ten times as compared with undoped silicon substrate (α=10–15μV/K).

Numerically controlled sacrificial plasma oxidation using array-type electrode toward high-throughput deterministic machining

Deterministic machining processes, in which the removal distribution is programmed on the basis of surface figure error, are used for fabricating ultra-precision optics. In these processes, numerically controlled (NC) machining is performed by the dwell-time control of a small removal spot by controlling the scan speed of the work table. Although their accuracy is very high, their throughput is low because of the long path of a raster scan. Thus, we propose an array-type removal system that can control the dwell time to realise high-throughput deterministic machining. We focused on plasma-process-based deterministic methods, and NC sacrificial plasma oxidation was selected as the method for use in the prototype apparatus with an electrode array system. Using the system, the thickness range of the top silicon layer of a silicon-on-insulator wafer was successfully improved by the NC process, and it was demonstrated that the electrode array system can be used for deterministic machining.

A novel complementary N+-charge island SOI high voltage device

A new complementary interface charge island structure of SOI high voltage device (CNI SOI) and its model are presented. CNI SOI is characterized by equidistant high concentration n+ -regions on the top and bottom interfaces of dielectric buried layers. When a high voltage is applied to the device, complementary hole and electron islands are formed on the two n+-regions on the top and bottom interfaces. The introduced interface charges effectively increase the electric field of the dielectric buried layer (EI) and reduce the electric field of the silicon layer (ES), which result in a high breakdown voltage (BV). The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI. EI = 731 V/μm and BV = 750 V are obtained by 2D simulation on a 1-μm-thick dielectric layer and 5-μm-thick top silicon layer. Moreover, enhanced field EI and reduced field ES by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm, respectively.

Effects of the front surface field in n-type interdigitated back contact silicon heterojunctions solar cells

Abstract Previous simulations of interdigitated back contact silicon heterojunction (IBC-SiHJ) solar cells have indicated that front surface passivation is a critical factor in the performance of such cells. This is why we here focus on the effect of a front surface field (FSF) layer by 2D numerical modelling. A FSF layer made of a highly doped thin crystalline silicon top layer makes the cell performance insensitive to the surface recombination velocity up to quite high values (5000 cm/s). It also reduces the lateral resistance losses due to the increased lateral current through the doped layer particularly in IBC-SiHJ solar cells with large pitches. A FSF layer can also be produced by doped hydrogenated amorphous silicon due to the induced accumulation layer at the crystalline silicon surface. The positive effect of such layer strongly depends on the a-Si:H/c-Si interface quality.

Effects of size and defects on the elasticity of silicon nanocantilevers

The size-dependent elastic behavior of silicon nanocantilevers and nanowires, specifically the effective Young's modulus, has been determined by experimental measurements and theoretical investigations. The size dependence becomes more significant as the devices scale down from micro- to nano-dimensions, which has mainly been attributed to surface effects. However, discrepancies between experimental measurements and computational investigations show that there could be other influences besides surface effects. In this paper, we try to determine to what extent the surface effects, such as surface stress, surface elasticity, surface contamination and native oxide layers, influence the effective Young's modulus of silicon nanocantilevers. For this purpose, silicon cantilevers were fabricated in the top device layer of silicon on insulator (SOI) wafers, which were thinned down to 14 nm. The effective Young's modulus was extracted with the electrostatic pull-in instability method, recently developed by the authors (H Sadeghian et al 2009 Appl. Phys. Lett. 94 221903). In this work, the drop in the effective Young's modulus was measured to be significant at around 150 nm thick cantilevers. The comparison between theoretical models and experimental measurements demonstrates that, although the surface effects influence the effective Young's modulus of silicon to some extent, they alone are insufficient to explain why the effective Young's modulus decreases prematurely. It was observed that the fabrication-induced defects abruptly increased when the device layer was thinned to below 100 nm. These defects became visible as pinholes during HF-etching. It is speculated that they could be the origin of the reduced effective Young's modulus experimentally observed in ultra-thin silicon cantilevers.

Highly compact polarization-independent grating coupler

We propose a compact polarization-independent output grating coupler, which consists of T-shaped grooves. For only 20 periods on a silicon-on-insulator wafer with a 260nm thick top silicon layer, the output coupling efficiencies for both the TE and the TM modes are larger than 50% in the wavelength range of 1480-1580nm and are approximately 58% around 1550nm. The polarization-dependent loss of the device is within 0.05dB in the range of 1510-1580nm.