Toggle Rate Research Articles

A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN

This article proposes a low-power real-time hand gesture recognition (HGR) system with high recognition accuracy for smart edge devices. This design balances accuracy and power consumption by utilizing computation-efficient hybrid classifiers assisted with a majority voting scheme. By combining the recognition results of consecutive frames, the HGR system shows improved immunity to misclassification. In addition, the compressed input data before high-level processing dramatically reduce the on- chip memory and computational load. The proposed Edge-convolutional neural network (CNN) core with interactable processing engines reduces the memory accessing and the feature register toggling rate by 27% and 50%, respectively. The sequence analyzer based on majority voting improves the static and dynamic gesture recognition accuracy by ~7% and ~8% only with 9.4% hardware overhead. The test chip was fabricated in 65-nm CMOS technology, occupying the area of 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1.5 mm2. It consumes the lowest power of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$184~\mu \text{W}$ </tex-math></inline-formula> at 25 MHz and 0.6 V. The proposed HGR system can recognize six static gestures and 24 dynamic hand gestures with an average accuracy of 87.25%–95% and 85.4%–94.9%, respectively.

VLSI Architecture of DCT-Based Harmonic Wavelet Transform for Time–Frequency Analysis

The complex harmonic wavelet(CHW) is being used to directly compute frequency content with respect to time by employing discrete Fourier transform(DFT) and inverse discrete Fourier transform. However, DFT coefficients suffer severe leakage of energy from one band to another band of frequency. The leakage between bands is minimized by employing discrete cosine transform(DCT) in the harmonic wavelet transform, which leads to a better representation of the time-frequency spectrum. This paper introduces a new VLSI architecture for DCT-based harmonic wavelet for hardware implementation and prototyped on a commercially available virtex5 field-programmable gate array(xc5vlx110t). To validate the proposed implementation, its real-time captured results in the logic analyzer are verified with simulation results. The maximum operating frequency targeting the FPGA mentioned above device is reported as 114.34 MHz. The total On-Chip power of the above implementation is 1.102W, out of which 68mW is the dynamic power dissipation at a toggle rate of 12%. Finally, for the area utilization of the above implementation, its resource utilization targeting the above FPGA device is reported.

TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs

Energy-efficient processors are crucial for accelerating deep neural networks (DNNs) on edge devices with limited battery capacity. To reduce energy consumption, time-domain computing-in-memory (TD-CIM) is a splendid architecture, which consumes low computation and memory access energy due to low toggle rate of time-based signals and less data movements, respectively. When deploying DNNs in TD-CIMs, quantization is required, which has two types: uniform quantization (UQ) and nonuniform quantization (NUQ). To reach the same accuracy for one DNN, NUQ achieves smaller model size than UQ. Due to varying weight distributions across layers, mixed-precision quantization can further reduce model size, without degrading accuracy. However, previous TD-CIMs are inefficient for mixed-precision NUQ-DNNs due to their adopted bit-serial convolution increasing computation amount significantly. To address that, we propose a unique-weight convolution to accelerate mixed-precision NUQ-DNNs by a special kernel decomposition, reducing computation count remarkably. Based on that, we design a TD-CIM-based processor, TIMAQ, with three architectural techniques: 1) bit-cross-flipping-based kernel decomposer to reduce memory accesses and operations of decomposing kernels; 2) dual-mode-complementary predictor to remove redundant computations; and 3) activation-weight-adaptive pulse quantizer to decrease pulse quantization energy and error. Fabricated in 28-nm CMOS technology and tested on 1–8-b NUQ-DNNs, TIMAQ achieves 2.4–152.7-TOPS/W peak energy efficiency.

Ways to Reduce FPGA Power Supply by Software Methods

The paper is devoted to solving the problem of reducing the power consumption of programmable logic integrated circuits (hereinafter FPGAs) by software methods. The solution of this issue is especially relevant for various types of radio engineering systems, which include autonomous and portable stations. At the beginning of the paper, the theoretical foundations of FPGA consumption are given: types of consumption (static and dynamic) and influencing parameters (switching logic, the physical foundations of the integrated circuit and other internal resources). The work is explained and methodological guidelines are given for the specialized built-in PowerAnalyzer utility of the Quartus II software development environment, the main indicators with which the utility works are explained: toggle rate (switching frequency) and static probability (the probability of finding a signal in a stable state "0" or "1"). The following is a Pipelinning method for eliminating the racing effect (the effect in which signals passing through an element/crystal reach the destination point with different time delays). The essence of the method is that a register is set at the output of the element that creates the delay. The register stores the value at the input at the CLK clock frequency, so random switching of the previous circuit element will be ignored. This eliminates the effect of racing and reduces the dynamic consumption of the circuit. At the end of the paper, the results of reducing energy consumption using the above methods are presented. The greatest gain is observed when minimizing consumption, when a large number of logic elements on the FPGA chip are involved, as well as when high-frequency operation occurs. This is due to the fact that when using the methods of switching off the clock frequency, we get rid of a large number of switches between the states of logic elements (the higher the frequency, the more such state switches per unit of time). If the number of occupied elements is more than 50%, we get a reduction in power consumption of more than 5%, and if the number of occupied elements is 75%, then we get a gain of about 14%.

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

SRAM Stability Analysis and Performance–Reliability Tradeoff for Different Cache Configurations

Bias temperature instability (BTI), hot carrier injection (HCI), gate-oxide time-dependent dielectric breakdown (GTDDB), and random telegraph noise (RTN) degrade the stability of the deeply scaled transistors and the overall circuit reliability. These front-end wearout mechanisms are especially acute in the static random access memory (SRAM) cells of first-level (L1) caches, which are crucial for the performance of microprocessors due to frequent accesses. This article presents a methodology to analyze cache reliability degradation due to the combined effect of BTI, HCI, GTDDB, and RTN for different cache configurations, including variations due to associativity, cache line size, cache size, and the error-correcting codes (ECCs). Time-zero variability due to process and environmental parameters are also considered. First, we analyze how each wearout mechanism affects reliability degradation. Then we analyze the relationship between reliability (probability of failure) and performance (hit rate) of the L1 cache within a LEON3 microprocessor, while the LEON3 is running a set of benchmarks, which determine cell array activity, characterized by the duty cycle, toggle rate, temperature, and supply voltage distributions of cells. Insights on the performance-reliability tradeoff are provided for cache designers.

A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications

A novel type of highly efficient conditional feedthrough pulse-triggered flip-flop (P-FF) is proposed and demonstrated. The data-to-output (D-to-Q) delay in this circuit was highly optimized using predischarging and conditional signal feedthrough schemes. Power consumption was also reduced using a shared pulse generator and an output feedback-controlled conditional keeper, which diminished the floating status of the internal node. The driving strength of this design was further enhanced by including an additional pull-down path at the output node. Various postlayout simulation results applied to 16-nm FinFET technology demonstrated a higher energy efficiency (at all input data toggle rates) for the proposed topology than comparable P-FF devices. Notably, the proposed model achieved a 62% D-to-Q delay reduction, compared to a transmission gate FF, outperforming the device by more than 66% in terms of power efficiency and 87% in energy efficiency (at a 50% input data toggle rate). Improvements were even more significant in comparison with other conventional P-FFs. These results suggest the proposed design to be a viable new option for high-efficiency sequential elements in high-speed applications.

Implementation and Utilization of LBIST for 16 bit ALU

This paper refers to implementation of Low Power Built-In-Self-Test (LBIST) and its utilization for testing of 16 bit ALU core. Low Power Test Pattern (LP) Generator is programmable and able to produce pseudorandom test patterns. The programmability feature brings in selectiveness in toggling levels of test patterns. This helps to increase the error coverage gradient. This low power pattern generator consists of a pseudo random pattern generator (PSPR) which can be a linear feedback shift register or ring generator. The test pattern generator allows the production of binary sequences by devices with that selected toggling rate is defined as ‘Preselected toggling’ (PRESTO) activity. In this methodology, controls for operation of generator are selected automatically. Selection of all the controls is made simple and accurate for the tuning. Using this method fault coverage of test pattern generator can be improved as well as pattern count ratio gets improved. The proposed low power test compression method helps to get predictable test patterns. Here preselected toggling based logic BIST is used to get flexible and accurate test patterns hence high quality testing is achieved here with integration of PRESTO and LBIST method.

Eye Movements and Cognitive Strategy in a Fluid Intelligence Test: Item Type Analysis.

Eye movements help to infer the cognitive strategy that a person uses in fluid intelligence tests. However, intelligence tests demand different relations/rules tokens to be solved, such as rule direction, which is the continuation, variation or overlay of geometric figures in the matrix of the intelligence test. The aim of this study was to understand whether eye movements could predict the outcome of an intelligence test and in the rule item groups. Furthermore, we sought to identify which measure is best for predicting intelligence test scores and to understand if the rule item groups use the same strategy. Accordingly, 34 adults completed a computerized intelligence test with an eye-tracking device. The toggling rate, that is, the number of toggles on each test item equalized by the item latency explained 45% of the variance of the test scores and a significant amount of the rule tokens item groups. The regression analyses also indicated toggling rate as the best measure for predicting the score and that all the rule tokens seem to respect the same strategy. No correlation or difference were found between baseline pupil size and fluid intelligence. Wiener Matrizen-Test 2 was demonstrated to be a good instrument for the purpose of this study. Finally, the implications of these findings for an understanding of cognition are discussed.

Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip

A 3D stacked network-on-chip (NOC) promises the integration of a large number of cores in a many-core system-on-chip (SOC). The NOC can be used to test the embedded cores in such SOCs, whereby the added cost of dedicated test-access hardware can be avoided. However, a potential problem associated with 3D NOC-based test access is the emergence of hotspots due to stacking and the high toggle rates associated with structural test patterns used for manufacturing test. High temperatures and hotspots can lead to the failure of good parts, resulting in yield loss. We describe a unicast-based multicast approach and a thermal-driven test scheduling method to avoid hotspots, whereby the full NOC bandwidth is used to deliver test packets. Test delivery is carried out using a new unicast-based multicast scheme. Experimental results highlight the effectiveness of the proposed method in reducing test time under thermal constraints.

An Enhanced Adaptive Recoding Rotation CORDIC

The Conventional Coordinate Rotation Digital Computer (CORDIC) algorithm has been widely used in many applications, particularly in Direct Digital Frequency Synthesizers (DDS) and Fast Fourier Transforms (FFT). However, CORDIC is constrained by the excessive number of iterations, angle data path, and scaling factor compensation. In this article, an enhanced adaptive recoding CORDIC (EARC) is proposed. It uses the enhanced adaptive recoding method to reduce the required iterations and adopts the trigonometric transformation scheme to scale up the rotation angles. Computing sine and cosine is used first to compare the core functionality of EARC with basic CORDIC; then a 16-bit DDS and a 1,024-point FFT based on EARC are evaluated to demonstrate the benefits of EARC in larger applications. All the proposed architectures are validated on a Virtex 5 FPGA development platform. Compared with a commercial implementation of CORDIC, EARC requires 33.3% less hardware resources, provides a twofold speedup, dissipates 70.4% less power, and improves accuracy in terms of the Bit Error Position (BEP). Compared to the state-of-the-art Hybrid CORDIC, EARC reduces latency by 11.1% and consumes 17% less power. Compared with a commercial implementation of DDS, the dissipated power of the proposed DDS is reduced by 27.2%. The proposed DDS improves Spurious-Free Dynamic Range (SFDR) by nearly 7 dBc and dissipates 21.8% less power when compared with a recently published DDS circuit. The FFT based on EARC dissipates a factor of 2.05 less power than the commercial FFT even when choosing the 100% toggle rate for the FFT based on EARC and the 12.5% toggle rate for the commercial FFT. Compared with a recently published FFT, the FFT based on EARC improves Signal-to-Noise Ratio (SNR) by 8.9 dB and consumes 7.78% less power.

An Improved Methodology for Resilient Design Implementation

Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to (ii) improve design performance (e.g., timing speculation). However, significant overheads (e.g., 16% and 14% energy penalties due to throughput degradation and additional circuits) are incurred by existing resilient design techniques. For instance, resilient designs require additional circuits to detect and correct timing errors. Further, when there is an error, the additional cycles needed to restore a previous correct state degrade throughput, which diminishes the performance benefit of using resilient designs. In this work, we describe an improved methodology for resilient design implementation to minimize the costs of resilience in terms of power, area, and throughput degradation. Our methodology uses two levers: selective-endpoint optimization (i.e., sensitivity-based margin insertion) and clock skew optimization. We integrate the two optimization techniques in an iterative optimization flow which comprehends toggle rate information and the trade-off between cost of resilience and margin on combinational paths. Since the error-detection network can result in up to 9% additional wirelength cost, we also propose a matching-based algorithm for construction of the error-detection network to minimize this resilience overhead. Further, our implementations comprehend the impacts of signoff corners (in particular, hold constraints, and use of typical vs. slow libraries) and process variation, which are typically omitted in previous studies of resilience trade-offs. Our proposed flow achieves energy reductions of up to 21% and 10% compared to a conventional (with only margin used to attain robustness) design and a brute-force implementation (i.e., a typical resilient design, where resilient endpoints are (greedily) instantiated at timing-critical endpoints), respectively. We show that these benefits increase in the context of an adaptive voltage scaling strategy.

Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.

Mapping Based Energy Efficient Counter Design on FPGA

— In this work, 8-bit counter power optimized counter is designed with help of energy efficient techniques called mapping and simulation activity file in format of Value Change Dump (VCD) file and setting file (*.xpa) to define toggle rate, activity rate and enable rate for the power consumption estimation in order to get energy efficient design. With mapping, there is 33.33%, 34.61%, 36.5%, 36.49%, 36.86%, 36.9% dynamic power reduction in counter when device is operating on 10MHz, 100MHz, 1GHz, 10GHz, 100GHz and 1 THz frequency. This reduction achieved by mapping control signal to control port in place of mapping control signal to LUT (Look Up Table) input. In Resource utilization, when we are mapping the control signal to control port, there is 70.58% less number of LUT and 39.89% less number of IO usage than mapping the control signal to LUT inputs. Spartan-3 FPGA is taken as target device and Xilinx 14.1 ISE is taken as design, synthesis and implementation tools. Verilog HDL(Hardware Description Language) is used to synthesize the counter on FPGA. The power dissipation of the FPGA based energy efficient design is verified using Xilinx XPower tool.

SU‐E‐J‐59: Effective Adaptive DMLC Gated Radiotherapy with OAR Sparing

Purpose:Patient respiratory motion degrades the effectiveness of cancer radiation treatment. Advanced respiratory gating delivers radiation dose accurately yet with elongated treatment time. The goal of this research is to propose a novel adaptive dMLC dynamic gating with high delivery efficiency and precision.Methods:The dose delivery of dMLC is aided by simultaneous tracking of tumor and organ at risk (OAR). The leaf opening/closing will follow the motion trajectory of the tumor while sparing the OAR. The treatment beam turns on only when there is no overlapping between OAR and tumor in BEV. A variety of evaluation metrics were considered and calculated, including duty cycle, beam toggling rate, and direct irradiation avoidance to OAR, under various combinations of different tumor margins and the distance between the centers of the tumor and OAR in BEV (expressed as dx).Results:Retrospective simulation was performed to investigate the feasibility and superiority of this technique using four groups of synchronized tumor and OAR motion data. The simulation results indicate that the tumor and OAR motion patterns and their relative positions are the dominant influential factors. The duty cycle can be greater than 96.71% yet can be as low as 6.69% depending different motion groups. This proposed technique provides good OAR protection, especially for such cases with low duty cycle for which as high as 77.71% maximal direct irradiation to OAR can be spared. Increasing dx improves the duty cycle (treatment efficiency) and provides better OAR volume sparing, whereas, that of the tumor margins has the opposite influence.Conclusion:This real‐time adaptive dMLC gated radiation treatment with synchronous tumor and OAR tracking has inherent accurate dose delivery to tumor with reduced treatment time. In addition, the OAR protection capability make it an outstanding potential treatment strategy for mobile tumors.

High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions

Since hash functions are cryptography's most widely used primitives, efficient hardware implementation of hash functions is of critical importance. The proposed high performance hardware implementation of the hash functions used sponge construction which generates desired length digest, considering two key design metrics: throughput and power consumption. Firstly, this paper introduces unfolding transformation which increases the throughput of hash function and pipelining and parallelism design techniques which reduce the delay. Secondly, we propose a frequency trade-off technique which can give us a scope of frequency value for making a trade-off between low dynamic power consumption and high throughput. Finally, we use load-enable based clock gating scheme to eliminate wasted toggle rate of signals in the idle mode of hash encryption system. We demonstrated the proposed design techniques by using 45 nm CMOS technology at 10 MHz. The results show that we can achieve up to 47.97 times higher throughput, 6.31% delay reduction, and 13.65% dynamic power reduction.

SU-E-J-137: Hybrid EOE and EOI Dynamic Gating for Effective Image Guided Radiation Treatment

Purpose: Respiratory gating can potentially reduce normal tissue complications and increase tumor local control, however, with prolonged treatment delivery time. To enhance the efficiency of beam delivery, dynamic hybrid gating approaches have been proposed. Methods: Three approaches have been proposed and they are differ when to update the gating window. (1) to update the gating window whenever a peak EOI (end-of-inhale) is not in the current gating window; (2)to update the gating window whenever a new peak EOI is identified, where weighting factors will be used to determine gating window position. The variations of the sliding windows of previously acquired data used in gating window determination have also been investigated. Evaluation metrics, including duty cycle, beam delivery time, beam toggling rate, and their changes have been quantified and compared along with static EOE (end-of-exhale) gating and static hybrid EOE-and-EOI gating. Results: Simulated over motion data of 400 treatment fractions from 15 patients have been performed. For static gating, gating window sizes of 2, 3, 4, and 5 mm have been performed. Duty cycles of both EOE and EOI gating increase with the gating window sizes, with EOE gating triples EOI gating. The beam toggling rate of EOI gating is lower than that of EOE gating. With hybrid dynamic gating, the mean beam delivery time was decreased by more than 25% from static EOE gating to static hybrid gating and over 5% from static hybrid gating to dynamic hybrid gating. The average beam toggling rate increased within 20% from static EOE gating to static hybrid gating and decreased over 5% from static hybrid to dynamic hybrid gating. Comparison of the three dynamic hybrid gating approaches showed that there was no significant difference among them. Conclusion: The dynamic hybrid gating will improve the accuracy of gated radiation treatment and reduce gated treatment time.

Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

A thermal–mechanical coupled finite element model with experimental temperature verification for vertically stacked FPGAs

Back end of line 3D integration of dies is a promising technology that can allow for considerable boost in inter-chip communication and reduction in form factor of a package. This can result in, however, high die temperatures, particularly for multi-tier FPGAs, due to the high density of power dissipating circuits. Therefore, to design thermally aware multi-tier FPGAs, there is a need to first understand the relationship among circuit architectures, toggle rates, layout, clock frequency, I/O behavior, power, temperature, thermal stress, and thickness of inter-die substrates. This study investigated the relationship among these parameters as tested on a Spartan 3E-250K FPGA. The power-temperature simulations have been conducted on a model built in ANSYS finite element package. The model predictions have been verified by thermocouple-measured case temperatures. The verified model has been extended to predict the temperature and stress distributions for a 2-tier, stacked package.

Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits

This paper presents a novel and accurate method of estimating the toggle rates of signals in field-programmable gate array (FPGA)-based logic circuits without the use of simulation vectors. Compared to previous vectorless techniques, our approach provides improved accuracy-of-results, especially for individual signals, which could be leveraged by computer-aided design (CAD) tools for performing power optimization of logic circuits. Increased accuracy is achieved by using stochastic methods that estimate the transition densities at FPGA logic elements while accounting for both spatial and temporal correlation of logic signals. Spatial correlation is calculated by leveraging a unique XOR-based decomposition technique that provides both accurate results and fast computation times. We also consider the delay information of implemented circuits, providing for a comprehensive treatment of glitches, including the effects of inertial limits on power dissipation. Our toggle-rate estimation approach has been tested on a commonly used set of Microelectronic Center of North Carolina circuits, as well as a set of industrial circuits targeted to Altera Stratix II FPGAs. Results show that our techniques provide a three times lower percent error, while maintaining a low processing time, when compared to two existing techniques: the vectorless estimation tool shipped with the commercial Quartus II 8.0 CAD tool, and the ACE v2.0 academic tool produced from the University of British Columbia, Vancouver, BC, Canada.