Timing Closure Problems Research Articles

Optimized Lossless Embedded Compression for Mobile Multimedia Applications

Power consumption is a critical design factor in modern mobile chip design, in which the memory system with dynamic random-access memory (DRAM) consumes more than half of the entire system’s power. Without DRAM bandwidth compression, extreme multimedia operations such as 8K high dynamic range (HDR) recording and 8K video conference calling are not possible without sacrificing image quality or trimming because of thermal limitations or battery time sustainability constraints. Since heterogeneous processors are substantially involved in managing various types of fallbacks or software solutions, complicated compression algorithms for high-compression ratios are not actually adaptable owing to timing closure problems or high throughput requirements. In this paper, we propose evaluation metrics to assess lossless embedded compression (LEC) algorithms to reflect realistic design considerations for mobile multimedia scenarios. Furthermore, we introduce an optimized LEC implementation for contemporary multimedia applications in mobile devices based on the proposed metrics. The proposed LEC implementation enhances the compression ratio of LEC algorithms in other commercial application processors for contemporary premium smartphones by up to 9.2% on average, while maintaining the same timing closure condition.

Interconnect Solutions for Virtualized Field-Programmable Gate Arrays

Contemporary datacenters are enhancing their compute capacity, power efficiency, and processing latency by integrating field-programmable gate arrays (FPGA). One would like to virtualize FPGAs to share them between multiple users and to be able to allocate incoming tasks to FPGAs without interrupting their operation. To virtualize FPGAs, their complexities, such as board-specific system-level integration and tricky I/O timing closure problems should be abstracted away from users. To this end FPGA designers have proposed the shell concept which abstracts away the board-specific details from the user and provides an easy-to-use interface to the user application. In this paper, we create several shells using a wide variety of interconnect solutions and rigorously evaluate them in terms of accelerator frequency, usable bandwidth, area-efficiency, latency, wire demand, and FPGA routing congestion. We show that virtualization of four accelerators per chip with traditional bus-based FPGA interconnect costs an average frequency drop of 24%, increases the wire demand of the shell to 2.78X, and creates significant routing congestion. We also show that while FPGA-optimized soft network on chip interconnect solutions can mitigate the reduction in accelerator frequency, they exacerbate the wire demand and routing congestion problems and offer a lower usable bandwidth. Finally, we demonstrate that hard networks on chip are a superior interconnect solution for virtualized FPGAs in all of the aforementioned evaluation criteria making them well-suited to datacenter-optimized FPGAs.

A new local clock generator for globally asynchronous locally synchronous MPSoCs

The evolution of technology into deep sub-micron domains leads to increasingly complex timing closure problems to design multiprocessor systems. One natural alternative is to resort to the globally asynchronous, locally synchronous paradigm. This work proposes a generic architecture for very low power- and area-overhead local clock generators (LCGs) to drive processors, network-on-chip routers and other intellectual properties (IPs). As one original contribution, the article details the design of a digitally controlled oscillator (DCO) which is the core of the LCG architecture. This DCO was designed using a CMOS 65 nm technology. It produces at least 16 distinct frequencies from 117 MHz to 1 GHz and supports clock gating and glitch-free frequency changes. The DCO design is robust to process, voltage and temperature variations, takes 850.6 µm2 and dissipates up to 197 µW. The article also proposes an LCG controller to improve frequency accuracy for IPs which require more accurate timing. Designed in the same technology, the controller takes 2250 µm2 and consumes 130 µW in typical conditions, or 160 µW, under worst-case conditions.

Critical-path-aware high-level synthesis with distributed controller for fast timing closure

Centralized controllers commonly used in high-level synthesis often require long wires and cause high load capacitance, and that is why critical paths typically occur on paths from controllers to data registers instead of paths from data registers to data registers. However, conventional high-level synthesis has focused on delays within a datapath, making it difficult to solve the timing closure problem during physical synthesis. This article presents hardware architecture with a distributed controller, which makes the timing closure problem much easier. A novel critical-path-aware high-level synthesis flow is also presented for synthesizing such hardware through datapath partitioning, register binding, and controller optimization. We explore the design space related to the number of partitions, which is an important design parameter for target architecture. According to our experiments, the proposed approach reduces the critical path delay excluding FUs by 29.3% and that including FUs by 10.0%, with 2.2% area overhead on average compared to centralized controller architecture.

Scheduling and Resource Binding Algorithm Considering Timing Variation

The timing closure problem (e.g., meeting timing/clock period constraint) is one of the most important problems in the design automation. However, the rapid increase of the impact of the process variation on circuit timing makes the problem much more complicated and unpredictable to tackle in synthesis. This paper addresses a new problem of high-level synthesis (HLS) that effectively takes into account the timing variation. Conventional HLS may simply avoid the timing variation problem by considering the worst case or constant delay model of hardware resources, which are certainly not viable solutions. To overcome the impact of timing variation in HLS, this paper addresses the following two problems: 1) how can the statistical static timing analysis (SSTA) used in logic synthesis be modified and effectively applied to the delay and yield computation in HLS? and 2) how can scheduling and resource binding tasks effectively solve the HLS problem with the objective of minimizing latency under yield constraint? Through an extensive experimentation, we confirm that the proposed variation-aware HLS algorithm is able to reduce the latency by 19.7% under 90% performance yield constraint, compared with the result by conventional timing variation-unaware HLS .

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor

Iterative synthesis methods for making aware of wire congestion are proposed for a multi-context dynamically reconfigurable processor (DRP) with a large number of processing elements (PEs) and programmable-wire connections. Although complex data-paths can be synthesized using the programmable-wire, its delay is long especially when wire connections are congested. We propose two iterative synthesis techniques between a high-level synthesizer (HLS) and the place & route tool to shorten the prolonged wire delay. First, we feed back wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten by 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on the congestion. The synthesis time was shorten to 1/3 causing delay improvement rate degradation at two points on average.

A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures

As device feature size decreases, the reliability improvement against soft errors becomes quite necessary. A fault-secure system, in which concurrent error detection is realized, is one of the solutions to this problem. On the other hand, average interconnection delays exceed gate delays which leads to a serious timing closure problem. By using regular-distributed-register architecture (RDR architecture), we can estimate interconnection delays very accurately and their influence can be much reduced even in behavioral-level design. In this paper, we propose a fault-secure high-level synthesis algorithm for an RDR architecture. In fault-secure high-level synthesis, a recomputation CDFG as well as a normal-computation CDFG must be scheduled to control steps and bound to functional units. Firstly, our algorithm re-uses vacant areas on RDR islands to allocate new function units additionally for the recomputation CDFG. Secondly, we propose an efficient edge-break algorithm which considers comparison nodes' scheduling/binding. We can have small-latency scheduling/binding for both the normal CDFG and recomputation CDFG. Our algorithm reduces the required control steps by up to 53% compared with the conventional approach.

Compositionality of Statically Scheduled IP

Timing Closure in presence of long global wire interconnects is one of the main current issues in System-on-Chip design. One proposed solution to the Timing Closure problem is Latency-Insensitive Design (LID) [Luca Carloni, Kenneth McMillan, and Alberto Sangiovanni-Vincentelli. Theory of latency-insensitive design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20(no. 9):pp. 1059–1076, 2001; Mario R. Casu and Luca Macchiarulo. A new approach to latency insensitive design. In DAC'04: Proceedings of the 41st annual conference on Design automation, pages 576–581, New York, NY, USA, 2004. ACM Press].It was noticed in [Mario R. Casu and Luca Macchiarulo. A new approach to latency insensitive design. In DAC '04: Proceedings of the 41st annual conference on Design automation, pages 576–581, New York, NY, USA, 2004. ACM Press] that, in many cases, the dynamically scheduled synchronisations introduced by latency-insensitive protocols could be computed off-line as a static periodic schedule. We showed in [Julien Boucaron, Jean-Vivien Millo, and Robert De Simone. Latency-insensitive design and central repetitive scheduling. In Formal Methods and Models for Co-Design, 2006. MEMOCODE'06. Proceedings. Fourth ACM and IEEE International Conference on, pages 175–183, Piscataway, NJ, USA, 2006. IEEE Press; Julien Boucaron, Jean-Vivien Millo, and Robert De Simone. Formal methods of scheduling for latency-insensitive designs. EURASIP journal on embedded system, 2007 (not yet published)] how this schedule could then be used to further optimize the protocol resources when they are found redundant. The purpose of the present paper is to study how the larger blocks, obtained as synchronous components interconnected by LID protocols optimized by static schedule informations, can be again made to operate with an environment that provides also I/O connections at its own (synchronous or GALS) rate.We also consider the case of multirate SoC, using results from SDF (Synchronous DataFlow) theory [Edward A. Lee and David G. Messerschmitt. Synchronous data flow. Proceeding of the IEEE, vol. 75(no. 9):pp. 1235–1245, 1987].

Clustering for Processing Rate Optimization

Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have timing closure problems at post-layout stages due to the emergence of multiple-clock-period interconnects. Consequently, a tradeoff between clock frequency and throughput may be needed to meet the design requirements. In this paper, we find that the processing rate, defined as the product of frequency and throughput, of a sequential system is upper bounded by the reciprocal of its maximum cycle ratio, which is only dependent on the clustering. We formulate the problem of processing rate optimization as seeking an optimal clustering with the minimal maximum-cycle-ratio in a general graph, and present an iterative algorithm to solve it. Experimental results validate the efficiency of our algorithm

No clock, no bus - no sweat [asynchronous IC interconnect network

This article presents a UK start-up which believes it has come up with a fundamental shift in interconnection technology that will solve timing closure problems in complex chips. It is based on an asynchronous design and uses packet switching technology. It is expected to be particularly effective in SoC design.

Timing Challenges for Very Deep Sub‐Micron (VDSM) IC

Many IC design houses failed to be market leaders because they miss the market window due to timing closure problems. Compared to half‐micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis. However, interconnect delays are unknown until the wire geometry is defined in physical design. Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately. Delay estimates for individual nets (global nets, long wires, large fan‐outs, buses), which matter most for the critical paths can be inaccurate and cause a design failure. Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high‐performance product and potentially larger costs due to lost market share. Full‐chip, sign‐off verification with silicon‐accuracy will allow these problems to be discovered and fixed before tape‐out.