Timing Analysis Methodology Research Articles

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time (t). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre-and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre-and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in Eldo SPICE environment with 65 nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

Analysis of the Impact of Electrical and Timing Masking on Soft Error Rate Estimation in VLSI Circuits

Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. An accurate SER evaluation is provided based on a SPICE-oriented electrical masking analysis, combined with a TCAD characterization process. Furthermore, the proposed work analyzes the effect of a Static Timing Analysis (STA) methodology and the actual interconnection delay on SER evaluation. An analysis of the generated Single Event Multiple Transients (SEMTs) and the circuit operating frequency that are related to the SER estimation is also discussed. Various benchmarks, synthesized utilizing a 45 nm and 15 nm technology, are employed, and the experimental results demonstrate the SER variation as the device node scales down.

Extinguishment of cable fires at packaged transformer substations

Introduction. According to the statistical data, electrical fires account for the majority of all fire accidents. Hence, better fireproofing of fuel and energy facilities is a relevant issue. The article addresses electrical fire extinguishment using high-expansion foam. An extinguishment time analysis methodology, applicable to fire extinguishment using high-expansion foam, has been developed to validate these solutions. The purpose of this article is to calculate the dependence between the fire extinguishment time and the foam consumption rate. The research objectives are to 1) identify the principal values to be used in the calculations and the list of input data; 2) to identify the dependence between the extinguishment time and the foam consumption rate using packaged transformer substation 2BKTP (1,000 kVA) as an example. Calculation methodology. The calculation methodology is based on the material balance equation between the amount of foam, applied for firefighting purposes, and the amount of foam, destroyed as a result of its contact with the heated wire surface, which is the main fire load inside burning electrical facilities. Research results. The co-authors have calculated the fire suppression time using packaged transformer substation 2BKTP (1,000 kVA) as an example. Dependencies between fire extinguishment time, specific foam consumption rate, and foam application rate are identified. Conclusions. The co-authors have identified the main values, needed to simulate a fire extinguishing model. They have also shown optimal foam consumption and application rates and offered their assessment of the applicability of high-expansion foam to electrical fires.

Graph-based STA for asynchronous controllers

We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its additional requirement over STA is a graph-based Event Model, Marked Graph or Petri Net. We contrast STA, ASTA results for 23 asynchronous circuit benchmarks, and demonstrate significant timing differences between the ASTA critical cycle and STA critical path, with cut cycles. We also demonstrate our correlation to SPICE level simulations, for 20 of the 23 circuits. Our ASTA flow effectively upper bounds critical cycle delay over SPICE, and is orders of magnitude faster.

Devulcanisation of ground rubber tyre by novel ternary deep eutectic solvents

This study aims to optimize the parameters in thermo-sonic devulcanisation of ground rubber tyre (GRT) with the help of three novel ternary deep eutectic solvents (TDESs). Ultrasonic frequency and time were varied between 37 and 80 kHz and 25–60 min, respectively. Whereas, heating temperature and time intervals were ranged from 25 to 200 °C and 0–60 min. Through one factor at a time (OFAT) analysis and response surface methodology (RSM) software modelling, the study shows that 37 kHz sonication for 60 min and thermal treatment at 180 °C for 55 min were the optimum conditions, resulting in 75% devulcanisation (%Dvul). At these conditions, devulcanisates were further analysed by thermogravimetric analyser (TGA), Fourier transform infrared spectroscopy (FTIR), swelling behaviour and Horikx curve to verify the occurrence of devulcanisation. These additional analyses verify that the intensity of sulphur bridges reduced and negligible changes in degradation temperature as well as the amount of main chain scission were experienced. These evidences demonstrate selective scission of sulphur-bridges as well as the high potential that polymeric properties were being retained compared to typical reclamation process.

Takt Time Analysis in Lean Six Sigma: From Conventional to Integration

Lean Six Sigma offers a comprehensive roadmap, tools and technique for continuous business process improvement. Principally, Lean Six Sigma integrates Lean’s principle of “value” and “speed” with Six Sigma’s “consistency” (i.e. variation reduction) concept into the DMAIC (Design, Measure, Analyze, Improve, Control) framework. The integration of Lean and Six Sigma advances the pace of business process improvement. Conceptually, Lean and Six Sigma must be applied side by side from both management (i.e. soft practices) and technical (i.e. hard practices) perspectives. However, empirical research found that prior studies on Lean Six Sigma tends to focus on the study of integration from the soft perspective, such as exploring and confirming the determinants for Lean Six Sigma success as well as the application of Lean Six Sigma processes within varies business environments. There is lack of study on the integration of Lean Six Sigma from hard perspective. Hence, the concept of how Lean and Six Sigma tools could be integrated remains ambiguous because there are no standard guideline that available. As such, based on a Lean Six Sigma project(of minimizing new students registration cycle time)that conducted in one of local private university as single case study, this paper explores how Lean and Six Sigma tools could be integrated based on Lean Six Sigma principle, with the focus on a Lean’s tool, namely “Takt Time Analysis”. Finding from the study suggested that Takt Time Analysis could be expanded from “Lean-based” tools to as “Lean Six Sigma tool” by including process variation and process capability as parameters for analysis. The finding as well as the LSS based Takt Time Analysis methodology developed in this study has descriptive value in terms of studying the integration of Lean and Six Sigma tools that govern continuous business process improvement via Lean Six Sigma.

Methodology for Timing and Impact Analysis of Signalized Intersections

A detailed procedure for capacity analysis of signalized intersections was first produced in 1976 and presented at the TRB Annual meeting (Bang, Hansson, Peterson 1978). In the eighties computer aids (named CAPCAL) based on this methodology were developed including traffic as well as safety and emission performance measures for different types of at-grade intersections. Capcal has been continuously updated since then, the last version CAPCAL 4.1 was based on a major Swedish HCM project called METKAP 2009 – 2013. The theoretical basis for the calculation procedures as well as the software are still subject to revisions based on user inputs. National base parameters and other variables are also included in these updates. CAPCAL 4 also adds improved capabilities to visualize calculation results. The use of CAPCAL is mandatory in projects for the Swedish National Road Authority, and it is also commonly used by local authorities, consultants and universities in Sweden.The computational methodology for signalized intersections is based on an iterative process including the following functions for each calculation cycle:Determination of saturation flow for all types of unopposed or opposed discharge. Traffic flow distribution between lanes in the same sub-approach.Identification of the critical conflict point for traffic streams that are served by different main signal phases (Min∑_1^n▒q/s).Signal timing for minimum total delay or other object function.Determination of traffic performance at normal and oversaturated conditionsSpecial consideration has been devoted to development of the following sub modules: Automatic calculation of inter-green times and minimum green periods which give instant feedback of geometry changes Short lane utilization and contribution to approach bottleneck capacity. Procedure for identification of the critical conflict point for complex intersection configurations and phase schemes including extra or alternative phases for efficient discharge of turning movements.Optimal signal timing including considerations to minimum green and lost time restraints Consideration of exit capacity Calculation of delay and other traffic performance variables for forcasted traffic flows including improved handling of oversaturation Linking of capacity model to existing modules for calculating impact on environment, costs and traffic safety.The method is limited to isolated intersections, and based on fixed timed signals. Impacts of Traffic Actuated signal control is approximated by signal timing corrections (max green, green time extension intervals) based on traffic simulation results for different types of control strategies. In further work those corrections will be enhanced and also include the impacts of bus priority in vehicle actuated signal control using a more complex probability based model.

A new class of seismic damage and performance indices for arch dams via ETA method

Quantifying the progressive failure of concrete dams under seismic excitation is essential to risk assessment. This paper addresses this timely topic through Endurance Time Analysis (ETA) methodology coupled with the concepts of Damage Index (DI) and Performance Index (PI). This newly proposed framework is computationally effective in determining engineering demand parameters in dam-reservoir-foundation system. This is achieved through the selection of over twenty single-variable DI and PI based on displacement, joint movement, crack ratio and dissipated energy. ETA and capacity functions are derived, and results are quantitatively compared.

Survival Analysis in LGD Modeling

The paper proposes an application of the survival time analysis methodology to estimations of the Loss Given Default (LGD) parameter. The main advantage of the survival analysis approach compared to classical regression methods is that it allows exploiting partial recovery data. The model is also modified in order to improve performance of the appropriate goodness of fit measures. The empirical testing shows that the Cox proportional model applied to LGD modeling performs better than the linear and logistic regressions. In addition a significant improvement is achieved with the modified "pseudo" Cox LGD model

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (VT) variation, already a significant issue in today's advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local VT variation and achieve a reliable design with minimal pessimism.

A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis

A novel methodology for accurate and efficient static timing analysis is presented in this paper. Our methodology uses the traditional cell library table structure with one modification. The cell library tables are filled with the gate output signal moments instead of the gate output 50% delay and output slew. Using only few moments gives much better accuracy and visibility for the gate output waveform than using the time domain information. Simple convolution of the gate output moments with the interconnect moments yields the signal moments at the stage output. The parameters of the gate input signal, which are used for the table access of the successive stage, are directly computed from the predecessor stage output moments using the closed form expressions without having to explicitly transform the frequency domain moments to time domain. Thus, the interconnects and the gates are treated in a unified moment-based homogeneous framework. The proposed approach inherits the classical cell library tables approach efficiency with even reduced computation complexities. As compared to the classical cell library table approach, the proposed approach accounts for the increasingly nonlinear and non-monotonic waveform shapes which are prohibitively difficult to represent in the classical approaches. In contrary to the classical approaches, increasing the accuracy in the novel approach is made flexible and can be achieved by simply using more moments. To illustrate the concept and prove its merits, multiple examples are presented with 2-3 moments which maintain accuracy within 1%-3% as compared to SPICE.

Completion Time Dynamics Of Doctoral Studies At Makerere University: A Hazard Model Evaluation

Issues related to attrition and completion time of graduate studies are certainly an internationally challenging and important area of higher education literature. In this paper, completion time dynamics of doctoral studies at Makerere University were investigated based on data extracted for all 295 candidates in the commencement cohorts from 2000 to 2005. The total elapsed time, from first enrollment to submission of a final copy of a thesis, was adopted as a measure of completion time and event history (survival) analysis methodology was applied. Results reveal a median completion time of 5.0 years. Following a Cox model, in a range of candidate, candidature, discipline and institutional variables, the rate of completion was higher for candidates at younger ages during commencement, international students, those registered in science-related disciplines, and those in commencement cohorts from 2000 to 2002. The model correctly identified the order of completion times by about 72% of the time.

Static timing analysis for modeling QoS in networks-on-chip

Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource allocation are major concerns for system designers. In particular, a model for the properties of packet delivery through the network is desirable. We present a methodology for packet-level static timing analysis in NoCs. Our methodology quickly and accurately gauges the performance parameters of a virtual-channel wormhole NoC without simulation. The network model can handle any topology, link capacities, and buffer sizes. It provides per-flow delay analysis that is orders-of-magnitude faster than simulation while being significantly more accurate than prior static modeling techniques. Using a carefully derived and reduced Markov chain, the model can statically represent the dynamic network state. Usage of the model in a placement optimization problem is shown as an example application.

Survival Analysis in LGD Modeling

The paper proposes an application of the survival time analysis methodology to estimations of the Loss Given Default (LGD) parameter. The main advantage of the survival analysis approach compared to classical regression methods is that it allows exploiting partial recovery data. The model is also modified in order to improve performance of the appropriate goodness of fit measures. The empirical testing shows that the Cox proportional model applied to LGD modeling performs better than the linear and logistic regressions. In addition a significant improvement is achieved with the modified “pseudo” Cox LGD model.

Timing analysis of scan design integrated circuits using stimulation by an infrared diode laser in externally triggered pulsing condition

This paper presents a new timing analysis methodology for clock driven scan design integrated circuits, based on externally triggered pulsed laser stimulation. The laser pulse can easily be shifted to time windows of interest in reference to clock and scan pattern. It is demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a time resolution correlated to the signal switching time, offering new opportunities to failure analysis.

Voltage-Aware Static Timing Analysis

Static timing analysis (STA) techniques allow a designer to check the timing of a circuit at different process corners, which typically include corner values of the supply voltages as well. Traditionally, however, this analysis only considers cases where the supplies are either all low or all high. As will be demonstrated, this may not yield the true maximum delay of a circuit because it neglects the possible mismatch between the supplies of successive gates on a path. A new methodology for timing analysis is proposed, where, in a first step, the critical paths of a circuit are identified under an assumption that all the supply nodes are independent of one another, thus allowing for mismatch between the supplies. Then, given these critical paths, the authors incorporate into the analysis the relationships between the supply node voltages by considering the power grid that they are tied to, and refine the worst case time delay values on a per-critical-path basis. This refinement is posed as a sequence of optimization problems where the operation of the circuit is abstracted in terms of current constraints. The authors present their technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids

Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

In this paper we address both empirically and theoretically the impact of an advanced manufacturing phenomenon on the performance of high-speed digital circuits. Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18-/spl mu/m CMOS process. The measured data revealed a significant systematic, rather than random spatial intrachip variability of MOS gate length, leading to large circuit path delay variation. The delay of the critical path of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. We demonstrate explicitly that intrachip Lgate variation has a significant detrimental impact on the overall circuit performance, shifting the entire distribution of clock frequencies toward slower values. This is in striking contrast to the impact of interchip Lgate variation, traditionally considered in statistical circuit analysis, which leads to the variation of chip clock frequencies around the average value. Moreover, analysis shows that the spatial, rather than proximity-dependent systematic Lgate variability, is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows mitigation of the detrimental effects of Lgate variability and have developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of practical implementation of the methodology, and provide guidelines for managing design complexity.

Timing Analysis and Optimization for DSM IC—Guest Editorial

Timing analysis and optimization is one of the key areas in modern VLSI design and has become bottleneck in designing multi-million gate systems. Consequently, computer-aided design research in this area has shown in a new renaissance after the advent of deep sub-micron IC technology and the accompanying restrictive performance constraints. Effects related to interconnect dominance has resulted in technical problems in areas such as floorplanning, placement, routing and performance prediction, and therefore has made accurate and effective timing analysis and optimization more challenging. The current special issue of VLSI DESIGN Journal is devoted to papers that provide high-quality ideas and results in critical areas related to the timing analysis and optimization for deep sub-micron IC. The first paper called, “Timing Challenges for Very Deep Sub-Micron (VDSM) IC” is by Lin et al. The paper presents current and future timing challenges for VDSM IC. It presents why traditional design flow failed in timing sign-off and how silicon-accurate timing tools are necessary to overcome timing challenges and limitations that cause timing convergence and capacity problems in VDSM IC technology. The second paper is by Dhaou et al. Its title is “Energy Efficient Signaling in DSM Technology.” The key idea is to combat crosstalk noise and to reduce the power consumption while driving the global wire at an optimal delay by reducing voltage swing with buffer insertion and resizing. In 0.25mm CMOS, over 60% of energy-saving can be achieved if supply voltage is reduced from 2.5 down to 1.5 V. The third paper is written by Chen et al., entitled “Simultaneous Buffer-Sizing and Wire-Sizing for Clock Tress Based on Lagrangian Relaxation.” In this paper, a Lagrangian relaxation algorithm for simultaneously optimizing delay, power, skew, area, and sensitivity in clock tree is presented. The effectiveness and accuracy of algorithm is demonstrated. The fourth paper is by Hu et al. Its title is “Performance Driven Global Routing Through Gradual Refinement.” The authors present a heuristic for interconnect global routing that can optimize routing congestion, delay and the number of bends that are oftenly competing objectives. In addition to exploiting timing constrained routing flexibility, a gradual refinement method is applied for simultaneous optimization on congestion, timing and the number of bends. Experiments on benchmarks confirm the effectiveness of this method. The fifth paper is written by Arunachalam et al and is entitled “Accurate Coupling-Centric Timing Analysis Incorporating Temporal and Functional Isolation.” This paper presents a timing analysis methodology TACO that can accurately bind the arrival times in the presence of coupling. The timing windows at the aggressor can be used to determine whether the aggressor can switch in conjunction with the victim. Results of industrial examples show that the proposed method actually helps in reducing pessimism in the timing analysis. The sixth paper is authored by Lee et al. and is entitled “CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization.” Generalized delay and power equations are proposed in this paper for CMOS circuit optimization achieved by transistor and interconnect minimization. The equations help analyze the entire power-delay trade-off with less complexity and fast computation time. The seventh paper is written by Huang and is entitled “Improving the Timing of Extended Finite State Machines via Catalyst.” In this paper, a timing optimization technique for a complex finite state machine that consists of random logic and data operator is presented. The proposed technique based on the concept of catalyst adds a functionally redundant block to the original circuit so the timing critical paths are divided for speed improvement. The eighth paper is by Huang et al. Its title is “TimingDriven-Testable Convergent Tree Adders.” The tree structure of adders is normally unbalanced and therefore generates high fanout in timing critical paths that may cause racing and increase the delay. A timing optimization

G-Nets: A petri net based approach for logical and timing analysis of complex software systems

When specifying, designing and analyzing complex systems, it is necessary to adopt a modular or compositional methodology. Such a methodology must allow the designer the ability to verify local logical and timing properties of individual modules or components in the system, and also allows the verification of the correct behavior of interacting components. The application of Petri nets for the modeling and verification of systems, at specification and design levels, are well known. Despite powerful structuring mechanisms available in the Petri nets theory for the construction of the model of complex systems, the designer is still likely to face the problem of state explosion when analyzing and verifying large systems. In this work we introduce a modular logical and timing analysis methodology for a kind of high level Petri net named G-Nets that can be applied for complex software systems.

Performance evaluation of concurrent systems using Petri nets

We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its additional requirement over STA is a graph-based Event Model, Marked Graph or Petri Net. We contrast STA, ASTA results for 23 asynchronous circuit benchmarks, and demonstrate significant timing differences between the ASTA critical cycle and STA critical path, with cut cycles. We also demonstrate our correlation to SPICE level simulations, for 20 of the 23 circuits. Our ASTA flow effectively upper bounds critical cycle delay over SPICE, and is orders of magnitude faster.