Times Higher Throughput Research Articles

GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

The past two decades have witnessed a revolution in the use of electronic devices in our daily activities. Increasingly, such activities involve the exchange of personal and sensitive data by means of portable and light weight devices. This implied the use of security applications in devices with tight processing capability and low power budget. Current architectures for processors that run security applications are optimized for either high-performance or low energy consumption. We propose an implementation for an architecture that not only provides high performance and low energy consumption but also mitigates security attacks on the cryptographic algorithms which are running on it. The proposed architecture of the Globally-Asynchronous Locally-Synchronous-based Low Power Security Processor (GALS-based LPSP) inherits the scheduling freedom and high performance from the dataflow architectures and the low energy consumption and flexibility from the GALS systems. In this paper, a prototype of the GALS-based LPSP is implemented as a soft core on the Virtex-5 (xc5-vlx155t) FPGA. The architectural features that allow the processor to mitigate Side-Channel attacks are explained in detail and tested on the current encryption standard, the AES. The performance analysis reveals that the GALS-based LPSP achieves two times higher throughput with one and a half times less energy consumption than the currently used embedded processors.

An embedded software-reconfigurable color segmentation architecture for image processing systems

Image segmentation is one of the first important and difficult steps of image analysis and computer vision and it is considered as one of the oldest problems in machine vision. Lately, several segmentation algorithms have been developed with features related to thresholding, edge location and region growing to offer an opportunity for the development of faster image/video analysis and recognition systems. In addition, fuzzy-based segmentation algorithms have essentially contributed to synthesis of regions for better representation of objects. These algorithms have minor differences in their performance and they all perform well. Thus, the selection of one algorithm vs. another will be based on subjective criteria, or, driven by the application itself. Here, a low-cost embedded reconfigurable architecture for the Fuzzy-like reasoning segmentation (FRS) method is presented. The FRS method has three stages (smoothing, edge detection and the actual segmentation). The initial smoothing operation is intended to remove noise. The smoother and edge detector algorithms are also included in this processing step. The segmentation algorithm uses edge information and the smoothed image to find segments present within the image. In this work the FRS segmentation algorithm was selected due to its proven good performance on a variety of applications (face detection, motion detection, Automatic Target Recognition (ATR)) and has been developed in a low-cost, reconfigurable computing platform, aiming at low cost applications. In particular, this paper presents the implementation of the smoothing, edge detection and color segmentation algorithms using Stretch S5000 processors and compares them with a software implementation using the Matlab. The new architecture is presented in detail in this work, together with results from standard benchmarks and comparisons to alternative technologies. This is the first such implementation that we know of, having at the same time high throughput, excellent performance (at least in standard benchmarks) and low cost.

Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames

In this paper we have presented a memory efficient architecture for 3-D DWT using overlapped grouping of frames. Proposed structure does not involve any line-buffer or frame-buffer for 1-level 3-D DWT. It involves only a frame-buffer of size O(MN) to compute multilevel 3-D DWT, unlike the existing folded structures which involve frame-buffer of size O(MNR) . The saving of line-buffer and frame-buffer by the proposed structure for the implementation of first-level DWT is of substantial advantage, since the frame-size is very often as large as 1920 × 1080 and frame-rate varies from 15 to 60 fps. The proposed structure has a small cycle period, and offers small output latency compared to the existing structures. Compared to the best of the available designs, the proposed design involves significantly less memory words. For frame-size 17 × 144 and frame-rate 60 fps, the proposed structure involves 7.96 times less memory words and involves 12.3% less average computation time (ACT) than the best of the existing folded designs. It involves 4.28 times less memory words than the recently proposed parallel design. The synthesis result for frame-size 176 × 144 and frame-rate 60 fps for the FPGA device 6VLX760FF1760-2 shows that the proposed structure involves 9.6 times less BRAMs and offers 2 times higher throughput than the folded design. It involves 1.9 times less BRAMs than the parallel design and offers nearly same throughput rate. The proposed structure has significantly less slice-delay-product (SDP) and dissipates significantly less dynamic power than the existing structures.

A 1080p H.264/AVC Baseline Residual Encoder for a Fine-Grained Many-Core System

This paper presents a baseline residual encoder for H.264/AVC on a programmable fine-grained many-core processing array that utilizes no application-specific hardware. The software encoder contains integer transform, quantization, and context-based adaptive variable length coding functions. By exploiting fine-grained data and task-level parallelism, the residual encoder is partitioned and mapped to an array of 25 small processors. The proposed encoder encodes video sequences with variable frame sizes and can encode 1080p high-definition television at 30 f/s with 293 mW average power consumption by adjusting each processor to workload-based optimal clock frequencies and dual supply voltages-a 38.4% power reduction compared to operation with only one clock frequency and supply voltage. In comparison to published implementations on the TI C642 digital signal processing platform, the design has approximately 2.9-3.7 times higher scaled throughput, 11.2-15.0 times higher throughput per chip area, and 4.5-5.8 times lower energy per pixel. Compared to a heterogeneous single instruction, multiple data architecture customized for H.264, the presented design has 2.8-3.6 times greater throughput, 4.5-5.9 times higher area efficiency, and similar energy efficiency. The proposed fine-grained parallelization methodology provides a new approach to program a large number of simple processors allowing for a higher level of parallelization and energy-efficiency for video encoding than conventional processors while avoiding the cost and design time of implementing an application specific integrated circuit or other application-specific hardware.

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

In this paper, we present a modular and pipeline architecture for lifting-based multilevel 2-D DWT, without using line-buffer and frame-buffer. Overall area-delay product is reduced in the proposed design by appropriate partitioning and scheduling of the computation of individual decomposition-levels. The processing for different levels is performed by a cascaded pipeline structure to maximize the hardware utilization efficiency (HUE). Moreover, the proposed structure is scalable for high-throughput and area-constrained implementation. We have removed all the redundancies resulting from decimated wavelet filtering to maximize the HUE. The proposed design involves <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> pyramid algorithm (PA) units and one recursive pyramid algorithm (RPA) unit, where <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> = <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> =⌈log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P̅</i> ⌉ and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> is the input block size, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> , respectively, being the height and width of the image. The entire multilevel DWT is computed by the proposed structure in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MR</i> cycles. The proposed structure has <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> (8 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> ×2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> ) cycles of output latency, which is very small compared to the latency of the existing structures. Interestingly, the proposed structure does not require any line-buffer or frame-buffer, unlike the existing folded structures which otherwise require a line-buffer of size <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> ) and frame-buffer of size <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</i> /2× <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> /2) for multilevel 2-D computation. Instead of those buffers, the proposed structure involves only local registers and RAM of size <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</i> ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> ). The saving of line-buffer and frame-buffer achieved by the proposed design is an important advantage, since the image size could very often be as large as 512 × 512. From the simulation results we find that, the proposed scalable structure offers better slice-delay-product (SDP) for higher throughput of implementation since the on-chip memory of this structure remains almost unchanged with input block size. It has 17% less SDP than the best of the corresponding existing structures on average, for different input-block sizes and image sizes. It involves 1.92 times more transistors, but offers 12.2 times higher throughput and consumes 52% less power per output (PPO) compared to the other, on average for different input sizes.

High-throughput transaction executions on graphics processors

OLTP (On-Line Transaction Processing) is an important business system sector in various traditional and emerging online services. Due to the increasing number of users, OLTP systems require high throughput for executing tens of thousands of transactions in a short time period. Encouraged by the recent success of GPGPU (General-Purpose computation on Graphics Processors), we propose GPUTx , an OLTP engine performing high-throughput transaction executions on the GPU for in-memory databases. Compared with existing GPGPU studies usually optimizing a single task, transaction executions require handling many small tasks concurrently. Specifically, we propose the bulk execution model to group multiple transactions into a bulk and to execute the bulk on the GPU as a single task. The transactions within the bulk are executed concurrently on the GPU. We study three basic execution strategies (one with locks and the other two lock-free), and optimize them with the GPU features including the hardware support of atomic operations, the massive thread parallelism and the SPMD (Single Program Multiple Data) execution. We evaluate GPUTx on a recent NVIDIA GPU in comparison with its counterpart on a quad-core CPU. Our experimental results show that optimizations on GPUTx significantly improve the throughput, and the optimized GPUTx achieves 4-10 times higher throughput than its CPU-based counterpart on public transaction processing benchmarks.

High Profile Intra Prediction Architecture for UHD H.264 Decoder

This paper presents a new architecture for high profile intra prediction in H.264/AVC video coding standard. Our goal is to design an Intra prediction engine for 4Kx2K@60fps Ultra High Definition (UHD) Decoder. The proposed architecture can provide very stable throughput, which can predict any H.264 intra prediction mode within 66 cycles. Compared with previous design, this feature can guarantee the whole decoding pipeline to work efficiently. The intra prediction engine is divided into two parallel pipelines, one is used for 4x4 block prediction loops and the other is used to prepare data for MB loops. It can overlap data preparing time with prediction time, which can finish data loading and storing within 2 cycles. Comparing with MB pipeline only architecture, it can achieve more than 3.2 times higher throughput with 29.8K gates cost. The proposed architecture is verified to work at 175MHz for our UHD Decoder by using TSMC 90G.

HARNESSING THE POWER OF IDLE GPUS FOR ACCELERATION OF BIOLOGICAL SEQUENCE ALIGNMENT

This paper presents a parallel system capable of accelerating biological sequence alignment on the graphics processing unit (GPU) grid. The GPU grid in this paper is a desktop grid system that utilizes idle GPUs and CPUs in the office and home. Our parallel implementation employs a master-worker paradigm to accelerate an OpenGL-based algorithm that runs on a single GPU. We integrate this implementation into a screensaver-based grid system that detects idle resources on which the alignment code can run. We also show some experimental results comparing our implementation with three different implementations running on a single GPU, a single CPU, or multiple CPUs. As a result, we find that a single non-dedicated GPU can provide us almost the same throughput as two dedicated CPUs in our laboratory environment, where GPU-equipped machines are ordinarily used to develop GPU applications. In a dedicated environment, the GPU-accelerated code achieves five times higher throughput than the CPU-based code. Furthermore, a linear speedup of 30.7X is observed on a 32-node cluster of dedicated GPUs. We also implement a compute unified device architecture (CUDA) based algorithm to demonstrate further acceleration.

Systemic Characterization of Immune Suppression from Battlefield‐like Stress

This study was designed to determine impact of battlefield‐like stress on the immune response using whole genome profiling and computational analyses. We collected whole blood samples from 15 US Army Ranger Training Battalion cadets before, and after 5 and 8 weeks training. Genome wide transcriptomes were analyzed using oligo‐nucleotide arrays representing ~24,700 human genes. More than 2300 differentially regulated genes were identified at both time points. Ontological enrichment showed suppression of transcripts important in microbial pattern recognition, inflammation, chemotaxis, and antigen preparation and presentations. Profiled genes and pathways were confirmed using both quantitative real time PCR arrays and high throughput ELISAs. Our computational analyses (for regulatory motifs and networks) identified the stress response site (STRE) as common regulatory motif of a number of profiled genes. Though, population of mono‐nuclear cells was not changed significantly, in vitro exposure of leucocytes to Staphylococcus enterotoxin B, a pyrogenic toxin, showed no response, and they seemed anergic. This may mean a highly compromised protective immune response. Suppression of most molecules involved in antigen presentation and lymphocytes' activation pathways may explain why individuals or animal models exposed to chronic stress show poor response towards proteineous antigen based vaccines.We are grateful to DTRA for funding.

SOI optical microring resonator with poly(ethylene glycol) polymer brush for label-free biosensor applications

Label-free monitoring of biomolecular interactions has become of key importance for the emerging proteomics field. Monitoring real time interaction kinetics and high throughput screening of complex samples is of major importance for a variety of applications. We previously reported the use of Silicon-on-Insulator photonics microring resonators for cheap disposable biosensors on chip. Silicon photonics is a platform for micro- and nanoscale integrated devices that can be fabricated at extremely low cost, with standard CMOS processing facilities. Incorporation of a hydrophilic heterobifunctional polymer coating on the silicon chips largely improved the system's response to non-specific binding. We report the chemical coating procedure, the chemical surface characterization and optical measurements for both specific and non-specific interactions. Two heterobifunctional polymer coatings were investigated, α-sulfanyl-ω-carboxy-poly(ethylene glycol) and monoprotected diamino-poly(ethylene glycol). Homogenous coatings with thicknesses of 2.3 and 2.5nm were obtained, corresponding to a surface loading of 99pm/cm2 carboxy- and 97pm/cm2 aminogroups, respectively. The polymer coated sensor with covalently bound biotin receptor molecules showed very low response to Bovine Serum Albumin (BSA) up to 1mg/ml in contrast to a high response to avidin with much lower concentrations (2, 10, 87.5 and 175μg/ml). By extrapolation the detection limit is about 10ng/ml or 0.37fg avidin mass. Comparison with the values reported for standard silanization confirms the polymer coating does not deteriorate the system's limit of detection. This makes the optical biosensor chip suitable to be integrated in a microflow system for commercial label-free biosensors and for lab-on-a-chip applications.

SCTPmx: An SCTP Fast Handover Mechanism Using a Single Interface Based on a Cross-Layer Architecture

Recently, SCTP is attracting attention to support mobility in the Internet because it does not require additional equipment such as the Home Agent of Mobile IP. This paper focuses on an SCTP fast handover mechanism using a single interface because it is assumed that small mobile devices have a single interface per communication medium such as IEEE802.11b due to hardware limitations. The proposed mechanism called SCTPmx employs a cross layer control information exchange system called LIES to predict handover. LIES was originally designed to achieve network layer fast handover and then it was extended by adding the network layer primitives for efficient interaction among the link layer, the network layer, and the transport layer. Prior to handover, SCTPmx can generate a new address that will be used after handover and can execute duplicate address detection of IPv6. SCTPmx can suppress the delay caused by channel scanning at the link layer by employing selective background scanning mechanism which allows to continue data communication during channel scanning. In addition, SCTPmx can notify the correspondent node of the new address before handover. SCTPmx was implemented on FreeBSD. SCTPmx achieved better than 25 times lower handover latency (100 msec) and 2 times higher throughput than previous proposals.

Novel Batch Titanium Nitride CVD Process for Advanced Metal Electrodes

This article describes a novel CVD process for TiN films developed in a 300 mm Vertical Furnace. We have solved Chlorine incorporation at low temperature inside the TiN layer while at the same time the batch process yields a 3 times higher throughput per dual reactor system compared to a single wafer system with 3 chambers.We show process results for load sizes ranging from 5 to as much as 100 wafers that prove filler wafers are only required to a minimum. Applications of the developed TiN process in Metal-Insulator-Metal memory devices such as Deep Trench DRAM, Stack DRAM, as well as Control Electrodes in Charge trapping Flash memory

Studies on the passive-star-coupler architecture for optical-burst-switched networks

Considering the state of the art of wavelength conversion technology, it is likely to dictate a more limited and sparse deployment of wavelength converters in optical burst switching (OBS) networks. Without wavelength conversion capabilities at optical switches, how to avoid burst contention becomes an important issue. This paper proposes an approach to controlling wavelength-division-multiplexing passive optical stars, consisting in queuing arrivals for delayed reception, to be used in OBS networks. This solution brings optical star networks a step closer to all-optical realization. In addition, it allows almost total utilization of the channels, obtainable until now only by time-division multiplexing control. The proposed solution does not suffer performance degradation under heterogeneous traffic conditions and increasing number of nodes. It is thus unique in offering the potential for an all-optical solution and providing at the same time high throughput, low delay, small buffer requirements, and robustness under all traffic conditions.

High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells

This paper presents a high-performance asynchronous template, single-track full-buffer (STFB), which achieves close to full-custom performance using a standard cell design flow and industry standard CAD tools to perform schematic capture, simulation, cell layout, and automatic placement and routing. This template and flow is demonstrated and evaluated with the implementation of a 64-bit asynchronous prefix adder, and its test circuitry, using the TSMC 0.25-/spl mu/m process. The 64-bit asynchronous prefix adder layout requires 0.96 mm/sup 2/ and the entire 260-k transistor test chip reaches a measured throughput of 1.45GHz. The design demonstrates that the STFB template can yield three times higher throughput with approximately half of the area of comparable quasi-delay-insensitive (QDI) templates, requires less timing assumptions than ultra-high-speed GasP bundled-data circuits, and can be designed with an automated place and route flow.

Low Thermal Mass Gas Chromatography: Principles and Applications

In gas chromatography (GC), temperature programming is often considered to be the second most important parameter to control, the first being column selectivity. A radically new GC technology to achieve ultrafast temperature programming with an unprecedented cool down time and low power consumption has recently become available. This technology is referred to as low thermal mass GC (LTMGC). Though the technology has its roots in resistive heating, which forms the basis of principle and design concept, the approach taken to achieve ultrafast heating and cool down time by LTMGC represents a significant break-through in GC. Despite some rectifiable shortcomings, LTMGC has proven to be an ideal methodology to deliver near/real time GC data, high precision, and high throughput applications. It is a new approach for modern high-speed GC. This paper documents the fundamental design principles behind LTMGC, performance data, and examples of applications investigated.

Simultaneous Quantification of Terpenelactones and Flavonol Aglycones in Hydrolyzed Ginkgo biloba Extract by Liquid Chromatography with Inline Ultraviolet and Evaporative Light Scattering Detection

We report here a liquid chromatography (LC) method with inline ultraviolet/evaporative light scattering (UV/ELS) detection for the simultaneous quantification of the terpenelactones and flavonol aglycones in a single sample of hydrolyzed Ginkgo biloba extract (GBE). The sample is hydrolyzed by a rapid and convenient oven heating method for 1 h at 90 degrees C with 10% hydrochloric acid. The 1 h hydrolysis was found to be equivalent to the 2.25 h reflux treatment for dry powder extract, where total flavonol glycosides were 28.4 and 28.1%, respectively. Acceptable precision was achieved for total terpenelactones [relative standard deviation (RSD) = 4.8%] by ELS detection, and total flavonol aglycones (RSD = 2.3%) by UV detection. The analytical range was 1.5 to 7.3% (w/w) for the individual terpenelactones (ELS) and 2.5 to 15.0% (w/w) for the individual glycosides (UV) calculated from the aglycones quercetin, kaempferol, and isorhamnetin. This improved method allows for the first time high throughput sample preparation coupled with the quantification of the predominant compounds generally used for quality control of GBE in a single assay.

Network application programming interfaces (APIs) performance on commodity operating systems

Network Application Programming Interfaces (APIs) are important components of network-based applications. They play a central role in the end-to-end performance ultimately delivered by networked applications. In addition, most network architectures exploit the underlying networking APIs in their designs. We present an empirical performance evaluation on the PC platform of the most popular networking APIs, namely: Winsock/BSD, Java, and RMI.To explore the impact of the underlying operating system and the Java Virtual Machine architecture on the networking APIs, we conducted performance tests on four widely used operating systems namely, Windows NT 4.0, Windows 2000, Linux, and Solaris 8. We found that RMI latency is 1.7 times higher over Java. Latency over Java is around two to three times higher than over native Windows or BSD sockets. Moreover, native sockets yield around 1.8 and 3.5 times higher throughput over Java and RMI, respectively. We hope that our results will be useful to application designers and developers and help them better optimize the end-to-end performance of their applications with a knowledge of the performance of the underlying networking APIs.

Enzyme-linked immunosorbent assay for the measurement of JNK activity in cell extracts.

A colorimetric enzyme-linked immunosorbent assay (ELISA) for the measurement of kinase activity of c-Jun N-terminal kinases (JNKs) in cell extracts is described. The assay involves passive immobilisation of the substrate GST-cJun on the surface of a microtiter plate, selection of JNK protein kinases directly in substrate-coated wells, kinase reaction, and detection of substrate phosphorylation by a phosphoepitope-specific antibody. The ability of this assay to selectively measure JNK activity relies on the high-affinity interaction between JNKs and c-Jun. Accordingly, we found that JNKs could be captured on the microtiter plate surface through binding to the immobilised GST-cJun. Moreover, JNKs retained the specificity of their interaction with and phosphorylation of c-Jun with respect to the dependence on both intact docking domain and the dimerisation state of c-Jun. This novel procedure represents a marked improvement on conventional radioactive assays in terms of sensitivity, accuracy of evaluation, low time consumption, high throughput and amenability to automation. It is expected to be useful forthe acceleration and facilitation of JNK activity measurement in cell extracts, in particular for large-scale screening of clinical samples.

Integration of robots into intelligent control systems

States that intelligent manufacture requires robots to be quickly reprogrammed and reconfigured to differing manufacturing requirements. Key to this is the control system architecture. Proposes a control system utilizing three networks suitable for time critical, fast messaging and high throughput data respectively. Discusses the technologies to be used are discussed along with the functionality required.

An effective access control method for high‐speed local area networks and metropolitan area networks

AbstractThis paper proposes an access protocol with a high throughput for the ultrahigh‐speed local area network (LAN) and metropolitan area network (MAN) with the transmission capacity exceeding 100 Mbps. The slottedring configuration is suited to the access method for the ultrahigh‐speed LAN/MAN. Several protocols have been proposed, such as DQDB and ATMR, which, however, have problems in that the throughput in DQDB cannot reach the transmission capacity and the throughput in ATMR decreases when the traffic is nonuniform.In the proposed protocol, the reset signal circulates the ring and the fairness of the access is ensured by limiting the number of slots to be sent by each node by the window size. The number of slots to be sent is not limited if none of the downstream nodes has data to be sent. This helps to realize a high throughput independently of the traffic situation. As the result of performance evaluation, it is verified that the proposed protocol is useful in the following two points: (1) approximately 1.8 times higher throughput is realized compared to the existing protocols when the traffic concentrates to a particular node; and (2) the delay time is suppressed to a low value for burst traffic such as video.