With the process node (CMOS transistor size) becoming increasingly smaller, there is an ever-increasing need for the software to handle the large gate count with faster turnaround time and better accuracy. Reaching timing closure on multi-million gate VLSI chips using flat flow is infeasible due to hardware capacity limit, and excessive run time overheads. New flows and design implementations need to be introduced to manage the scalability of design sizes by scaling down the memory usage and run time. Traditionally, the flat implementation of designs was used for smaller designs with maximum accuracy. Then the hierarchical approach was introduced to better the run time and handle the millions of gates by partitioning and assembling. Through this paper, we are going to look at the various implementation flows and its artifacts viz. flat, traditional hierarchical, models, post assembly ECO, context views, feasibility flows . We are also going to look at a advances in the technology of timing graph reduction and physical data reduction that enables new flow implementations and can be applied to both hierarchical and flat methodologies.
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