Timed Automata Research Articles

Extending Particle Hopping Models for road traffic with Timed Automata

Particle Hopping Models (PHM) are discrete models employed to mimic vehicular traffic, protein transport mechanisms, granular flows and other extended dynamic systems. Despite their simplistic exclusion principle, PHM correctly reproduce many macroscopic phenomena. Currently, positions of simulated entities in a PHM are updated at distinct moments by random selection, sequential iteration or in parallel. We advance these techniques by developing two time-continuous PHM for traffic applications on one-dimensional lattices and two-dimensional chequerboard topologies. By employing Timed Automata (TA) to formulate temporal boundaries and guide the movement process, driver behaviour can be finely adjusted. Both models are equipped with several stochastic components which influence critical densities and transition progressions. The proposed models can emulate almost all discrete update schemes at the level of individual movements and reproduce all major macroscopic free-flow to jamming progressions.

Non-blocking Supervisory Control of Timed Automata using Forcible Events

Abstract Real-valued clocks make the state space of timed automata (TA) infinite. Conventional supervisory control synthesis techniques are only applicable to finite automata (FA). Therefore, to synthesize a supervisor for TA using conventional techniques, an abstraction of TA to FA is required. For many applications, the abstraction of real-time values results in an explosion in the finite state space. This paper presents a supervisory control synthesis technique applied directly to TA without any abstraction. The plant is given as a TA with a set of uncontrollable events and a set of forcible events that may preempt the passage of time. To obtain a non-blocking controlled system, a synthesis algorithm is proposed that delivers a supervisor (also as a TA) avoiding the blocking states. The algorithm works by (iteratively) strengthening the guards of edges labeled by controllable events and invariants of locations where time progress can be preempted by forcible events.

Latency Evaluation of SDFGs on Heterogeneous Processors Using Timed Automata

Synchronous Data Flow (SDF) is a graphical computation model used for analyzing digital signal processing and real time multimedia applications. In general, these applications have two primary performance metrics - throughput and latency. Latency is important in multimedia processing applications such as video-conferencing, Internet telephony and games since latency surpassing a specific limit results in poor quality of service (QoS). Past work had focused on computing the latency of SDF graphs on homogeneous multiprocessor platforms. In this paper, we present an approach to compute the latency of a static schedule for a given unfolding factor with an optimal throughput for an SDF graph on a heterogeneous multiprocessor platform using timed automata. We use timed automata as a semantic model to represent the system model, which includes a synchronous data flow graph and an execution platform. We use the UPPAAL model-checker to specify the resulting network of timed automata and compute the latency.

Adaptive Cruise Control with Timed Automata

Abstract An adaptive cruise control (ACC) system maintains the vehicle at the given target speed when there is no leading vehicle in the sensor range. On the other hand, in the presence of a leading vehicle, the system maintains a safe distance between the vehicles while driving as close as possible to the target speed. For such an automated system, besides meeting safety requirements, it is also important to provide a comfortable drive. In this paper, we develop a formal model for adaptive cruise control system based on timed automata and express specifications in temporal logics. The proposed model supports different acceleration levels. Parametric constraints govern the transitions to the states associated with acceleration levels. The proposed parameter optimization methods generate parameter valuations for particular driving styles while guaranteeing safety and the specifications over the target speed. Therefore, the resulting system is guaranteed to satisfy the requirements while the driver comfort is optimized. The models and the synthesis approach are illustrated with examples.

Using priced timed automata for the specification and verification of CSMA/CA in WSNs

Using priced timed automata for the specification and verification of CSMA/CA in WSNs

Deriving of Time Constants in Timed Automata for Hazard Transition Sequences for STAMP/STPA

Abstract In recent years, information systems have become large-scale and complicated. The demand for research on the cause analysis of information systems that can fail and the construction of countermeasures has been increasing. Systems Theoretic Accident Model and Processes (STAMP) is an accident model based on systems theory. STAMP has the feature that it can analyze not only failures of system components and human errors but also hazards caused by unsafe interaction between components and between components and humans. An analysis method based on the STAMP model System-Theoretic Process Analysis (STPA) is a method for analyzing in advance the possibility of a system accident for the interaction between a controller and a controlled device. As a preliminary study, we have performed STAMP/STPA to ‘Fallen Barrier Trap at Railroad Crossing,” which is an example of STAMP/STPA analysis. We have analyzed with the time automaton model checker UPPAAL in cooperation with STAMP Workbench, a STAMP/STPA support tool. From the preliminary study, we consider that the analysis procedure can be automated in order to reduce the burden on analysts. In this paper, we propose a method for deriving hazard transition sequences as a STAMP/STPA support method. Specifically, the model definition is described in STAMP Workbench, the method of deriving files that can be used in UPPAAL from the definition statement is described, and in order to automate model checking, the SAT/SMT solver is used. The constraints for the clock variables in each component are automatically derived. This paper describes a method for deriving the shortest path as a counterexample that does not satisfy the safety constraint equation by using the calculation method of the concrete value the constraints of and the binary search method. The proposed method is applied manually as the evaluation experiment. We confirmed that an effective sequence corresponding to some hazard scenarios derived by the conventional procedure could be derived.

A timed model for discrete event system identification and fault detection

We present in this paper a timed discrete event model for system identification with the aim of fault detection, called Timed Automaton with Outputs and Conditional Transitions (TAOCT). The TAOCT is an extension of a recent untimed model proposed in the literature, called Deterministic Automaton with Outputs and Conditional Transitions (DAOCT). Differently from the DAOCT, where only the logical behavior of the discrete event system is considered, the TAOCT takes into account information about the time that the events are observed, and, for this reason, it can be used for the detection of faults that cannot be detected by using untimed models, such as faults that lead the fault detector to deadlocks. The TAOCT represents the fault-free system behavior, and a fault is detected when the observed behavior is different from the behavior predicted by the model, considering both logical and timing information. A practical example is used to illustrate the results of the paper.

Efficient Tracing Methodology Using Automata Processor

Tracing or trace interface has been used in various ways to find system defects or bugs. As embedded systems are increasingly used in safety-critical applications, tracing can provide useful information during system execution at runtime. Non-intrusive tracing that does not affect system performance has become especially important, but unfortunately, the biggest obstacle to this approach was the vast amount of real-time trace data, making it challenging to address complex requirements with relatively limited hardware implementations. Automata processors can be programmed with a memory-like structure of automata and have a structure specific to streaming data, large capacity, and parallel processing functions. This paper promotes the idea of high-level system-on-chip monitoring using automata processors. We used a safety-critical pacemaker application in the experiments, described timed automata (TA)-based requirements, and tested intentionally injected 4,000 random failures. The TA model converted for Automata Processor to monitor system, correctness, and safety properties achieved 100% failure detection rate in the experiment, and the detected failure is reported as fast enough to allow enough extent for failure recovery.

Movement authority security modeling and verification based on fault statechart

Communication Based Train Control System (CBTC) has become the development trend of train control system, and generating safe and reasonable movement authority is the key to ensure the normal operation of the whole system. Combined with the security of the system, a security analysis method based on fault tree information to construct fault Statechart is proposed. The fault tree that generates the abnormality of the movement authority is analyzed, and it is represented as a form that the Statechart can describe, thereby establishing a fault statechart of the movement authority generating abnormality. Finally, the formal modeling of the fault statechart is carried out by using the time automaton theory, and the fault state unreachable is taken as the attribute of the specification for inspection. The results show that the method of combining fault Statechart and time automata proposed in the paper is feasible and suitable for the analysis and verification of safety critical systems.

Conditional Simple Temporal Networks with Uncertainty and Resources

Conditional simple temporal networks with uncertainty (CSTNUs) allow for the representation of temporal plans subject to both conditional constraints and uncertain durations. Dynamic controllability (DC) of CSTNUs ensures the existence of an execution strategy able to execute the network in real time (i.e., scheduling the time points under control) depending on how these two uncontrollable parts behave. However, CSTNUs do not deal with resources. In this paper, we define conditional simple temporal networks with uncertainty and resources (CSTNURs) by injecting resources and runtime resource constraints (RRCs) into the specification. Resources are mandatory for executing the time points and their availability is represented through temporal expressions, whereas RRCs restrict resource availability by further temporal constraints among resources.
 We provide a fully-automated encoding to translate any CSTNUR into an equivalent timed game automaton in polynomial time for a sound and complete DC-checking.

A Flattening Algorithm for Hierarchical Timed Automata

We propose a coherent algorithm for the translation of hierarchical timed automata into networks of (planar) timed automata. This kind of translation is called flattening. The two types of timed automata are used in formal verification of real-time systems: systems of parallel interacting components whose execution essentially depends not only on the order of the events in the system, but also on the real time of these events. The concept of hierarchical timed automaton covers the syntactic variations that are used in existing studies and are non-comparable by their expressive power. The number of states in a flattened network of time automata is of the least order among the flattening results of existing studies.

Supervisory Energy-Management Systems for Microgrids: Modeling and Formal Verification

This article presents the modeling and verification of supervisory energy-management systems (EMSs) for microgrids using timed automata (TA) and a formal verification approach. The EMS plays an essential role in managing the power flow among different components in the microgrid system for its safe and reliable operation. The modeling of the EMS is based on predefined invariants with allowable and nonallowable operating modes, which are the conditions that do not change over time. The failure of invariants could have severe effects on microgrid system functionality, which highlights the importance of verification during the initial stage of EMS design. Conventional approaches, such as simulation and/or experimental verification, require manual checking and skilled professional knowledge to check EMS design correctness. Also, there may be a corner case that could lead to system failure that goes unidentified by manual analysis.

Formal Verification of Python Software Transactional Memory Based on Timed Automata

Formal Verification of Python Software Transactional Memory Based on Timed Automata

Методы и средства разработки автоматизированных информационных систем на основе онтологии «Управление качеством программно-технических комплексов»

The paper presents development and verification methods and means of requirements and design solutions formal models. They are intended to create complex critical automated information systems in a same model-language and information-software environment for all its participants. The development and verification processes are carried out in an automated way on the basis of subject-oriented ontologies. Ontologies describe the quality management processes of software and hardware complexes at the stages of requirements justification and system design. They are developing by means modeling and design languages SysML, FUML, OCL structures and mechanisms, the Petri nets mathematical apparatus, time automata and time logics. In order to execute of validation and verification for complex of requirements and design solutions, construction and model execution route analysis algorithms in the VM FUML virtual machine environment are developed. Integration and use methods for specialized verification tools CPN Tools, Rodin, SPIN and Modelica as means to automated testing of complex requirements and design solutions models are proposed. This complex provides more effective interaction between the customer and the contractor both in the development of requirements and in the design of the system, along with this, detection and provides limination of defects through the automated verification, validation and correction procedures implementation. This approach application will improve the quality of requirements and design solutions, as well as improve economic performance by reducing the financial and time costs, which associated with the implementation of additional work in the case of defects, and when changing requirements or operating conditions.

Minimum/maximum delay testing of product lines with unbounded parametric real-time constraints

Non-functional requirements like real-time behaviors are of ever-growing interest in many application domains of software product lines. Consequently, existing modeling formalisms and analysis techniques for reasoning about time-critical behaviors have to be adapted to product-line engineering, too. Featured timed automata (FTA) extend timed automata (TA) by feature constraints to enable efficient family-based verification of real-time properties. Here, we present configurable parametric timed automata (CoPTA) to further extend expressiveness of FTA by freely configurable and a-priori unbounded timing intervals of real-time constraints. Hence, CoPTA models impose infinite configuration spaces which makes variant-by-variant analysis practically infeasible. Instead, we present a family-based test-suite generation methodology for CoPTA models ensuring symbolical location coverage for every model configuration. Furthermore, we define a novel coverage criterion, called Minimum/Maximum Delay (M/MD) coverage, requiring every location in a CoPTA model to be reached by test cases with minimum/maximum possible durations, for systematically investigating best-case/worst-case execution times. We extend our family-based test-suite generation methodology to also achieve M/MD coverage on CoPTA models. Our evaluation results, obtained from applying our CoPTA tool to a collection of subject systems, reveal efficiency improvements of family-based test-suite generation, as compared to a variant-by-variant strategy in case of finite configuration spaces.

Safety-Assured Model-Driven Design of the Multifunction Vehicle Bus Controller

In this paper, we present a formal model-driven design approach to establish a safety-assured implementation of multifunction vehicle bus controller (MVBC), which controls the data transmission among the devices of the vehicle. First, the generic models and safety requirements described in International Electrotechnical Commission Standard 61375 are formalized as time automata and timed computation tree logic formulas, respectively. With model checking tool Uppaal, we verify whether or not the constructed timed automata satisfy the formulas and several logic inconsistencies in the original standard are detected and corrected. Then, we apply the code generation tool Times to generate C code from the verified model, which is later synthesized into a real MVBC chip, with some handwriting glue code. Furthermore, the runtime verification tool RMOR is applied on the integrated code, to verify some safety requirements that cannot be formalized on the timed automata. For evaluation, we compare the proposed approach with existing MVBC design methods, such as BeagleBone, Galsblock, and Simulink. Experiments show that more ambiguousness or bugs in the standard are detected during Uppaal verification, and the generated code of Times outperforms the C code generated by others in terms of the synthesized binary code size. The errors in the standard have been confirmed and the resulting MVBC has been deployed in the real train communication network.

A Study of Timed Automata for Self-Adaptive System

A Study of Timed Automata for Self-Adaptive System

An Innovative Approach for Modelling Urban Road Traffic Using Timed Automata and Formal Methods

Modelling and implementing adequate controllers for urban road traffic control constitute a huge challenge nowadays because of the complexity of systems, as well as possible scenarios and configurations, in each road in a city. A series of issues related to modelling these behaviours are common to arise when using formalisms, tools, and computation machines to perform complex calculations and limitations. This paper presents a formal, flexible, and adaptable approach, with no limitations, from the scientific point of view. For this purpose, modelling formalisms (cellular automata and timed automata) and analysis techniques (simulation and formal verification) are proposed to reach the main goals of modelling complex and adaptable behaviours in urban road traffic with multiple over time changeable configurations. A case study is presented, in order to illustrate the approach and demonstrate in detail the unlimited application of the presented approach.

Model checking Markov population models by stochastic approximations

Many complex systems can be described by population models, in which a pool of agents interacts and produces complex collective behaviours. We consider the problem of verifying formal properties of the underlying mathematical representation of these models, which is a Continuous Time Markov Chain, often with a huge state space. To circumvent the state space explosion, we rely on stochastic approximation techniques, which replace the large model by a simpler one, guaranteed to be probabilistically consistent. We show how to efficiently and accurately verify properties of random individual agents, specified by Continuous Stochastic Logic extended with Timed Automata (CSL-TA), and how to lift these specifications to the collective level, approximating the number of agents satisfying them using second or higher order stochastic approximation techniques.

Complexity of the characteristic semi-groups the direct products of „AG“ asynchronous automata of the strongly connected determined analogs the extensions associated with DFASC2 isomorfisms

The paper presents the assumption and the evidence is carried out of the direct product complexity of character-istic semi-groups of any number (“ ”) of deterministic, finite, asynchronous, highly consistent DFASC2. automata. The characteristic semi-group of the automaton interferes in the computational algorithm of the generalized homoeo-morphism of the automatons. Then determination the com-plexity of the characteristic semi-group enables to estimate the complexity of the computational generalized homoeo-morphism for the other classes of automatons. In the range of the mathematical model the conception of the determined analog of the extension of the automaton associated with the isomorphism g0, g1 ,…, gq-1 where q is the grade of the extensions, with the suitable assumptions it simulates the automaton variable in time. The variable automaton in time is the adequate mathematical model for the many technical and computational processes of the real time. The direct product of automatons can be considered as the realization- parallel calculations accordingly