Time-dependent Dielectric Breakdown Stress Research Articles

Investigation of the Combined Effect of Total Ionizing Dose and Time-Dependent Dielectric Breakdown on PDSOI Devices.

The combined effect of total ionization dose (TID) and time-dependent dielectric breakdown (TDDB) of partially depleted silicon-on-insulator (PDSOI) NMOSFET is investigated. First, the effect of TDDB on the parameter degradation of the devices was investigated by accelerated stress tests. It is found that TDDB stress leads to a decrease in off-state current, a positive drift in threshold voltage, and a reduction of maximum transconductance. Next, the degradation patterns of TID effect on the devices are obtained. The results show that the parameter degradation due to gamma radiation is opposite to the TDDB stress. Finally, the combined effect of TID and TDDB is investigated. It is found that the drift of the devices’ sensitive parameters due to TDDB stress decreases in a total dose of gamma radiation environment. The TDDB lifetime is shortened, but the pattern of gate current change remains unchanged. The failure mechanism of the gate oxide layer under TDDB stress is not changed after irradiation.

A multi-energy level agnostic approach for defect generation during TDDB stress

A multi-energy level agnostic model is used to examine defect generation during time-dependent dielectric breakdown stress. When considering distributed bond strengths, Monte Carlo simulations show that the distinctive power-law increase of the generated defects with stress time is attained. The rate is strongly influenced by the width of the distribution. The time to breakdown in DC and AC unipolar simulations is proportional to the fluence and energy of the injected carriers. These findings are in line with thin oxide breakdown measurements, which demonstrate a fluence and energy-driven process.

A multi-energy level agnostic simulation approach to defect generation

Defect generation during time-dependent dielectric breakdown stress is investigated by a multi-energy level agnostic model. Monte Carlo simulations show that the characteristic power-law increase of the generated defects with stress time is readily obtained when considering distributed bond strengths. DC and AC unipolar simulations show the proportionality between the time-to-breakdown and the fluence and energy of the injected carriers. These results are consistent with the experimental observations of a fluence and energy-driven process in thin oxides.

Anomalous TDDB Statistics of Gate Dielectrics Caused by Charging-Induced Dynamic Stress Relaxation Under Constant–Voltage Stress

Anomalous Time Dependent Dielectric Breakdown (TDDB) statistics of thick gate dielectrics, i.e., too large stress field/voltage dependence and nonlinear Weibull plot of TDDB lifetime, have been observed. Through the analysis of behaviors under the TDDB stress and also the comparison with thin gate dielectrics, it has been revealed that just the intrinsic charging of injected carriers to initial and stress-generated defects induces the dynamic stress relaxation under the constant–voltage stress, resulting in anomalous TDDB statistics. This charging-induced dynamic stress relaxation (CiDSR) effect reduces the validity of well-known Weibull statistics and prevents us from accurately predicting TDDB lifetimes utilizing various conventional scaling procedures, such as area, failure rate, and temperature scaling. Impact of the CiDSR effect increases with the thickness of gate dielectrics and the development of an appropriate lifetime prediction method is urgent not only for Si devices but also for various compound devices having thick gate dielectrics, such as GaN and SiC power devices.

ALD TaN Barrier for Enhanced Performance with Low Contact Resistance for 14nm Technology Node Cu Interconnects

We report on an alternative, atomic layer deposited (ALD) TaN barrier scheme for Cu interconnects for 14nm technology node and beyond, i.e., 64nm pitch and/or smaller interconnects. With VLSI integration requiring denser packing of interconnects, conformal fill of progressively narrower trenches and vias with high aspect ratio, presents tough challenge for line-of-sight physical vapor deposition processes. ALD overcomes these gap-fill challenges but has disadvantages of low throughput, chemical residues and relatively lower density of ALD barriers for effective blocking of O2and Cu diffusion. From gap-fill perspective, ALD films enable ultrathin, conformal barrier with reduced problems of overhang and large bottom thickness, typical of physical vapor deposited (PVD) films. Reduced bottom-thickness enables via-contact resistance reduction and less overhang improves gap-fill, while maximizing Cu volume in a trench/via structure. Our blanket film studies show that ALD films are 10-15% less dense compared to Ta-rich PVD films, and more importantly only desired low-resistance alpha-Ta nucleates on ALD films vs. thin PVD films. The conformality of ALD TaN as well as the nucleation of alpha-Ta on it form the basis of via contact resistance reduction, leading to performance enhancement.A plasma-enhanced ALD (PEALD) process helps increase density and improves the hermeticity of the barrier. But PEALD can cause dielectric damage and lead to TDDB failures especially in smaller technology nodes. To maximize density while protecting low-k dielectric during deposition and maintaining low-contact resistance, we explored different flavors and combinations of thermal (tALD) and plasma-enhanced ALD (PEALD). In this work, we use a new, commercially available 40 MHz direct-plasma ALD tool and corresponding optimized processes to maximize throughput and minimize dielectric damage. Different ALD flavors, viz., tALD+post plasma(PP) treatment, tALD/PEALD bilayer films were evaluated for 14 nm technology groundrule interconnects in k=2.7 and k=2.55 dielectric levels. We were able to achieve via contact resistance reduction of 25-35%, with equivalent or better performance for yield, defectivity and electromigration (EM), time-dependent dielectric breakdown (TDDB) and stress migration (SM) reliability. In-line measured defect density for dual-damascene interconnects in k=2.55 dielectric was studied with a conservative ALD TaN thickness process window; the splits with 15-20A of tALDPP TaN barrier layers were found to have the lowest defectivity. Similar data for various ALD splits vs. PVD showed that the same tALDPP process with a certain thickness combination of the bilayer TaN/ Ta resulted in least defect density. This same optimized condition looked best for viachain yield for a macro with ~108via links at 14nm groundrule. We also confirmed that the same condition resulted in the lowest via contact resistance for fully landed vias for 45 chiplets across 3 wafers; where via bottom size variation was <10%. Another study with several bilayer ALD splits in k=2.55 dielectric, showed that the 5tALD/5PEALD condition with initial tALD layer protecting the low-k dielectric followed by denser PEALD to get a more effective barrier, yielded better than PVD TaN. The lowest via resistance data was also recorded for the same split. The EM stress results for both via and line-depletion at each of k=2.7 and k=2.55 levels were also studied. ALD splits were slightly worse than PVD condition with the exception of one stress direction, but still pass reliability targets scaled from the 22 nm technology node. The kinetics data for via depletion tests results in activation energy in excess of 1 eV. TDDB stress results were obtained for builds in both k=2.7 and k=2.55 dielectrics. The most significant impact of ALD on TDDB was the restoration of voltage acceleration parameter (gamma) for both levels. Gammas (slopes of lines) for ALD of all three devices were clearly higher. This confirmed that our optimized ALD condition does no damage to the dielectric. Lastly, impact of different liner processes on stress migration (SM) was investigated at 225oC stress for 1000 hours. There were no stress fails on any of the liner splits from the traditional plate and nose type SM structures. In summary, ALD TaN is shown to be a robust alternative barrier for Cu interconnect technology for technologies nodes like 14nm and smaller. The process can be optimized to give ~30% reduction in via contact reduction while preserving healthy yield, defect density and EM, TDDB and SM reliability.

Electron fluence driven, Cu catalyzed, interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

During technology development, the study of low-k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model. Then we review several other low-k TDDB models that consider only intrinsic low-k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low-k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low-k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low-k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.

Estimates of EEPROM Device Lifetime

A method was developed to estimate EEPROM device life based on the consistency for breakdown charge, Q BD, for constant voltage time dependent dielectric breakdown (TDDB) and constant current TDDB stress tests. Although an EEPROM works with a constant voltage, Q BD for the tunnel oxide can be extracted using a constant current TDDB. Once the charge through the tunnel oxide, Δ Q FG, is measured, the lower limit of the EEPROM life can be related to Q BD/Δ Q FG. The method is reached by erase/write cycle tests on an EEPROM.

Measurement of Copper Drift in Methylsilsesquiazane-Methylsilsesquioxane Dielectric Films

Measurement of Cu drifts in methylsilsesquiazane-methylsilsesquioxane dielectric films in the presence of an electric field was conducted using bias-temperature stress (BTS) and capacitor-voltage (CV) analysis as well as time dependent dielectric breakdown (TDDB) stress. The amount of Cu ions in the dielectric films can be estimated making use of the flatband voltage shift ΔVFB from the BTS. Comparing the flatband voltage measured by CV analysis with the leakage current integrated over time, it is found that the main content of the leakage current during BTS is ionic current that can be attributed to the drift of Cu and mobile ions. The Cu ions cause the leakage current during TDDB stress to increase. The drift rate of Cu in methylsilsesquioxane is lower than the reported values in polyarylene ether (PAE) and fluorinated polyimide (FPI), and larger than that in plasma enhanced chemical vapor deposition (PECVD)-SiON.

Stress voltage polarity dependence of thermally grown thin gate oxide wearout

Gate oxide wearout for thermally grown 57-190-A SiO/sub 2/ films in a polycrystalline silicon-SiO/sub 2/-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm/sup 2/ constant current with positive and negative voltages at 250 degrees C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>