Time-dependent Dielectric Breakdown Model Research Articles

Automated reliability calculation of failure rate, lifetime extrapolation and prediction for embedded Metal-Insulator-Metal capacitors using an optimized Time-Dependent-Dielectric-Breakdown model

This study presents an algorithm for automated reliability analysis of embedded Metal-Insulator-Metal (MIM) capacitors with high-k dielectrics. With the proposed algorithm, Time-Dependent-Dielectric-Breakdown (TDDB) data of embedded capacitors of different physical dimensions measured at various stress conditions (temperature and electric field) can be analyzed in a uniform way based on a supervised learning approach. Instead of analyzing each influence parameter separately, the data is combined using automated linear regression, based on decision tree learning and thus defining a multi-dimensional plane. With this approach a simultaneous consideration of all affecting parameters and their interaction on the dataset can be achieved, while removing statistical outliers and extrapolating the reliability behavior of any failure percentage. To support the most common conduction mechanism related to the embedded ΜΙΜ capacitors, Poole-Frenkel emission, a new TDDB model with changed coordinate system is proposed.

The Gate Oxide Breakdown Failures of 4H-SiC MOS Devices

A study of Weibull distribution of 4H-SiC MOS capacitors has shown the effect of temperature as well as electric-field stress on the analysis of time-dependent breakdown. Time-Dependent Dielectric Breakdown (TDDB) is strongly electric-field dependent and temperature-dependent. In the paper, the test was at the stress level of 9.5, 10, and 10.5 MV/cm under 373K, through the TDDB model, the lifetime of the SiO2 can reach more than 30 years when the field pressure is not more than 6.6 MV /cm. The acceleration factor for TDDB (using E-Model) under different temperature stress, it expected that the capacitors would last for 2.28×107 years under 3MV/cm or 54 years under 6MV/cm at 373K.

Reliability of Wide Band Gap Power Electronic Semiconductor and Packaging: A Review

Wide band gap (WBG) power electronic devices, such as silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs) and gallium–nitride high-electron-mobility transistors (GaN HEMTs) have been widely used in various fields and occupied a certain share of the market with rapid momentum, owing to their excellent electrical, mechanical, and thermal properties. The reliability of WBG power electronic devices is inseparable from the reliability of power electronic systems and is a significant concern for the industry and for academia. This review attempts to summarize the recent progress in the failure mechanisms of WBG power electronic semiconductor chips, the reliability of WBG power electronic packaging, and the reliability models for predicting the remaining life of WBG devices. Firstly, the typical structures and dominant failure mechanisms of SiC MOSFETs and GaN HEMTs are discussed. This is followed by a description of power electronic packaging failure mechanisms and available packaging materials for WBG power electronic devices. In addition, the reliability models based on physics-of-failure (including time-dependent dielectric breakdown models, stress–strain models, and thermal cycling models), and data-driven models are introduced. This review may provide useful references for the reliability research of WBG power devices.

Life-time degradation of STT-MRAM by self-heating effect with TDDB model

Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising candidates for “universal memory” with the ultra-fast access speed, radiation resistance and theoretically unlimited endurance. However, there are many practical aspects that could degrade the life-time of STT-MRAM. In this paper, degradation on the life-time of the STT-MTJ device is observed experimentally, which is attributed to the so-called “self-heating effect” of the device. Simulation on the device is conducted on the self-heating effect to obtain the internal temperature inside the device. The self-heating effect of the STT-MTJ device is analyzed and its influence on the life-time degradation of the STT-MTJ is included in the time dependent dielectric breakdown model (TDDB, 1/E model). This inclusion should improve the accuracy of the estimation on the life-time.

Guest Editorial TDMR IIRW Special Section

The IEEE International Integrated Reliability Workshop (IIRW) is a unique event that takes place every year at the beautiful Fallen Leaf Lake, Tahoe, CA, USA. This workshop brings together reliability engineers and researchers from around the world, to exchange ideas over four days in a relaxed, friendly, and informal environment. The workshop focuses on the recent advances in research concerning semiconductor device reliability and its different challenges. Topics include transistor reliability [time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI), hot carrier (HC)], electromigration, chip-to-package interactions, emerging memory reliability, and many others. In 2018, IIRW hosted the inaugural Reliability Experts Forum where dozens of reliability experts around the world gathered in a day-long discussion to debate about the different reliability challenges facing advanced field-effect transistors (FETs). The first panel discussion focused on HC degradation. Moderated by Stanislav Tyaginov from imec, the HC discussion was initiated by Dr. Stew Rauch, presenting the energy-driven framework to explain hot carrier degradation. Next, Dr. Jen-Hao Lee presented an overview of HC degradation and self-heating challenges in advanced FinFETs, followed by Dr. Miaomiao Wang who presented HC effects in advanced CMOS devices 5 nm and beyond. Finally, Dr. Chetan Prasad from Intel presented some future areas of focus for HC degradation. The second panel was moderated by Prof. Luca Larcher and focused on TDDB. This discussion was started by Dr. Joe McPherson, who presented the field-driven electrochemical model, which was followed by Dr. Ernest Wu and a presentation of the energy-driven TDDB model and the clustering model. Dr. Chetan Prasad then presented an overview of TDDB in high-k advanced technology nodes. This panel also included Prof. Alex Shluger who presented an atomic level description of the defects and their generation process as it related to TDDB. Lastly, Prof. Kin Leong Pey presented his innovative work in physical characterization of dielectric breakdown. The last panel discussion focused on BTI and was moderated Dr. Jason Campbell. The discussion started with Dr. James Stathis, who introduced the topic and the various physics models that aim to explain BTI. Next, the reaction-diffusion based framework and BAT tool were presented by Prof. Souvik Mahapatra. Then, Prof. Tibor Grasser presented the defect centric framework followed by a detailed discussion of the two frameworks and their implications. Dr. Gennadi Bersuker then discussed the role of electron trapping/detrapping in BTI. Finally, Dr. Tanya Nigam talked about BTI from a circuit perspective, where she showed that no frequency dependence has been observed up to multiple Gigahertz of frequency. All three panel discussions simulated great discussions with the audience and brought up the points of consensus and differences in every topic, which helped provide many clarifications to different concepts.

Investigation of Switching-Induced Local Defects in Oxide-Based CBRAM Using Expanded Analytical Model of TDDB

The degradation behavior of Ag/SiO2-based conductive bridging RAM (CBRAM) is analyzed by conventional and expanded time-dependent dielectric breakdown (TDDB) models. By comparing the total cycling stress with time-to-breakdown ( ${t}_{\text {bd}}$ ) of the SiO2 used as a solid-electrolyte switching layer, it is clarified that the cycling stress does not reach the level at which dielectric breakdown of the SiO2 is triggered. On the other hand, we found that the ${t}_{\text {bd}}$ distribution after several cycles of set/reset stress agrees well with the simulated ${t}_{\text {bd}}$ distribution derived from expanded TDDB models, in which we assumed that a large amount of defects exists locally in the device area. This approach is useful for understanding the degradation in solid-electrolyte oxide of CBRAM.

Physics-Based Compact TDDB Models for Low- $k$ BEOL Copper Interconnects With Time-Varying Voltage Stressing

Time-dependent dielectric breakdown (TDDB) is one of the important failure mechanisms for copper (Cu) interconnects. This problem becomes more severe as the pitch between wires is shrinking and low-k dielectric materials (low electrical and mechanical strength) are used. Many TDDB models have been proposed based on different physics kinetics in the past. Recently, a physics-based TDDB model, which is based on the breakdown concept of electric path generation, has been proposed and has shown advantage over widely accepted existing electrostatic field-based TDDB assessment. However, determination of the time-to-failure from this model includes time-consuming finite-element method (FEM). In this paper, we try to mitigate this problem by developing fast time to failure evaluation method based on the closed form solution of the ion diffusion partial differential equations. We show that the location of the minimum concentration can be determined by the dominant terms with sufficient accuracy and the time to failure can also be computed with a few dominant terms. On top of this, we also consider the time-varying stressing voltages, which is commonly seen in practical VLSI chips. We propose to develop the equivalent dc stressing voltage, which is parameterized in terms of amplitude, duty cycle, and period for periodic stressing voltage waveforms using regression-based method. We further validate the proposed analytic TDDB concentration and time to failure formula, and the equivalent dc stressing voltage compact model against the results of an FEM analysis using COMSOL. Numerical results further show that the new compact TDDB model can lead to three orders of magnitude speedup with less than 1% error against the existing FEM results.

TDDB modeling depending on interfacial conditions in magnetic tunnel junctions

We investigated time-dependent dielectric breakdown (TDDB) modeling for MgO dielectrics with/without Mg insertion of MgO-based magnetic tunnel junctions (MTJs). The number of permanent trap sites at the no-Mg insertion interface was much larger than that at the Mg-inserted interface as determined by interval voltage stress (IVS) tests. The interfacial conditions related to trap sites at MgO dielectrics give rise to the different TDDB modeling. Here, we confirmed that the TDDB curves obtained from the constant voltage stress (CVS) tests for the Mg inserted interface case were well fitted by the power-law voltage V model, while the case of no-Mg inserted interface showed a good correlation to the 1/E model. The difference in the TDDB models related to interfacial conditions was understood based on theoretical and experimental results. Finally, we concluded that it is necessary to select an appropriate reliability model depending upon the presence or absence of the trap sites at dielectric interfaces.

A Study on Practically Unlimited Endurance of STT-MRAM

Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memory are by far the only known solid-state memory element that can realize a combination of fast read/write speed and high endurance. This paper presents a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases. A statistical study is conducted on the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, pulsewidth, duty cycle, and temperature. The experimental results coupled with TDDB models project $> 10^{15}$ write cycles. Furthermore, this work reports system-level workload characterizations to understand the practical endurance requirements for realistic memory applications. The results suggest that the cycling endurance of STT-MRAM is “practically unlimited,” which exceeds the requirements of various memory use cases, including high-performance applications such as CPU level-2 and level-3 caches.

Electron fluence driven, Cu catalyzed, interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

During technology development, the study of low-k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model. Then we review several other low-k TDDB models that consider only intrinsic low-k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low-k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low-k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low-k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.

Invasion percolation model for abnormal time-dependent dielectric breakdown characteristic of low-k dielectrics due to massive metallic diffusion

With the continuing aggressive scaling of interconnect dimensions and introduction of lower k materials, back-end-of-line (BEOL) dielectric time-dependent dielectric breakdown (TDDB) reliability margin is greatly reduced. In this paper, a comprehensive investigation on abnormal low-k TDDB characteristics, a systematic degradation of Weibull slopes, and a systematic increase of field acceleration at lower stress voltages due to massive Cu diffusion were conducted for Cu interconnect with low-k dielectric. Based on data from extensive electrical and physical analysis, such abnormal TDDB characteristics were attributed to slow metallic diffusion in bulk low-k under bias and temperature stress. A TDDB model based on invasion percolation was proposed to model the observed abnormalities. Cu interconnects with robust liner and capping layer, to ensure metal free low-k film, have become important for BEOL low-k TDDB.

Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells

The optimization of the programming voltage and the dimensions of antifuse bitcells is a design challenge due to antagonistic parameters. An optimization approach is presented using a time-dependent dielectric breakdown (TDDB) model. Fowler-Nordheim wear-out current and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> power-law models are identified using electrical characterizations performed on antifuse bitcells fabricated in standard 40-nm CMOS. The TDDB model allows the calculation of the programming voltage according to a targeted <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> and the antifuse bitcell dimensions. As a result, it was shown that the lowest programming voltage is obtained for a small capacitor, whereas the size of the drift transistor has a second-order impact.

A time dependent dielectric breakdown model for field accelerated low-k breakdown due to copper ions

We have previously shown that the choice of J(t,L)=0 boundary condition in the model of copper ion drift causes an internal field enhancement at the cathode due to the accumulation of copper ions. The ultimate breakdown of the dielectric occurs due to a combination of the field increase exceeding the intrinsic breakdown strength as well as the intrinsic bond breakage due to thermal and field effects. Here, we show that the field dependence of the intrinsic bond breakage shows an E2 dependence in the presence of copper ions enabling an excellent fit to the failure data on Cu∕SiO2∕Si devices.

Field Acceleration Model for TDDB: Still a Valid Tool to Study the Reliability of Thick $\hbox{SiO}_{2}$-Based Dielectric Layers?

The aim of this paper is to investigate the reliability of thick oxides that are dedicated to the power integrated device fabrication. The field dependence of defect-related time-dependent dielectric breakdown (TDDB) mode over a wide range of oxide thickness T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OX</sub> and electric field E, using multiple wafer fabrication lots, is investigated. TDDB tests are conducted under constant current injection using structures with different areas. For that, we have applied a new electric field model based on a 1/E model (reciprocal field dependence) that is proposed recently in the literature. We show that when the dielectric thickness increases, this electric field acceleration model gives an erroneous prediction of the long-term reliability. We conclude that it is too early to give a generalized law of dielectric to predict their reliability without taking into account the influence of thicknesses. Consequently, the 1/E model may therefore have to be revised.

Simple model for time-dependent dielectric breakdown in inter- and intralevel low-k dielectrics

A simple physical model is applied to time-dependent dielectric breakdown failure in ultralow-k(k=2.3) interlevel dielectrics. The model assumes that failure depends on the probability that an electron will have enough energy to damage the dielectric as it is accelerated in an electric field. It is seen that the characteristic form of the dependence of failure time on voltage or electric field is primarily dependent on the probability of having sufficient energy and not on the precise physical mechanism causing damage. An argument for a log-normal-like failure distribution is also presented.

Reliability of 100 nm silicon nitride capacitors in an InP HEMT MMIC process

A reliability study has been conducted on capacitors made with 100 nm of silicon nitride, in an InP HEMT MMIC fabrication process. Special wafers were fabricated, containing 1482 200 × 200 μm 2 capacitors each, and these were probed automatically. They were subject to ramped-voltage stress and the breakdown voltages recorded. On a typical wafer the vast majority of the breakdown voltages are between 50 and 90 V. In addition, IV curves were measured on a small number of specimens from 0 V up to breakdown. This was done in two regimes: above 25 V with a conventional setup, and below 25 V with an ultra-low-current measurement system. These were done at 25 and 175 °C above 25 V, and at 25 °C only below 25 V. The data were fitted well with a model for the conductivity, consisting of ohmic conduction at low voltages and Frenkel–Poole conduction at high voltages. Parameters of the fits included thermal activation energies, the voltage acceleration factor in the Frenkel–Poole model, and d eff, the effective thickness of the dielectric at the thinnest point. Analysis invoked the time-dependent dielectric breakdown model, which provides the time to failure as a function of the d eff, while d eff can be found from the ramped-voltage measurements. From the 10 wafers that have been probed so far, the mean of the distribution of failure times (at 1.5 V, 40 °C) is above 5 × 10 7 h, and the distribution becomes insignificant below 2 × 10 6 h. Further, the probability of failure in 10 years at 1.5 V, 40 °C is much less than 1 in 14,600. This indicates that 100 nm silicon nitride capacitors in this technology have good reliability.

Physics and Chemistry of Intrinsic Time-Dependent Dielectric Breakdown in SiO2Dielectrics

A molecular physics-based complementary model, which includes both field-induced and current-induced degradation mechanisms, is used to help resolve the E versus 1/E time-dependent dielectric breakdown (TDDB) model controversy that has existed for many years. The Complementary Model indicates either the E or 1/E–TDDB model can be valid for certain specified field, temperature, and molecular bonding-energy ranges. For bond strengths <3 eV, the bond breakage rate is generally dominated by field-enhanced thermal processes at lower fields and elevated temperatures where the E-model is valid. At higher fields, lower temperatures and higher bond strengths the bond breakage mechanism must be hole-catalyzed and the TDDB physics is described well by the 1/E-model. Neither the E-model nor 1/E-model works well for oxide thickness below tox < 4 nm where direct tunneling effects dominate in these hyper-thin films. The increase in DT leakage leads to more hole injection and trapping in the SiO2. This enhanced dielectric degradation rate with tox reduction can be easily incorporated into the Complementary Model where hole capture serves to catalyze Si–O bond breakage.

PHYSICS AND CHEMISTRY OF INTRINSIC TIME-DEPENDENT DIELECTRIC BREAKDOWN IN SiO2 DIELECTRICS

A molecular physics-based complementary model, which includes both field-induced and current-induced degradation mechanisms, is used to help resolve the E versus 1/E time-dependent dielectric breakdown (TDDB) model controversy that has existed for many years. The Complementary Model indicates either the E or 1/E–TDDB model can be valid for certain specified field, temperature, and molecular bonding-energy ranges. For bond strengths &lt;3 eV, the bond breakage rate is generally dominated by field-enhanced thermal processes at lower fields and elevated temperatures where the E-model is valid. At higher fields, lower temperatures and higher bond strengths the bond breakage mechanism must be hole-catalyzed and the TDDB physics is described well by the 1/E-model. Neither the E-model nor 1/E-model works well for oxide thickness below tox &lt; 4 nm where direct tunneling effects dominate in these hyper-thin films. The increase in DT leakage leads to more hole injection and trapping in the SiO 2. This enhanced dielectric degradation rate with tox reduction can be easily incorporated into the Complementary Model where hole capture serves to catalyze Si–O bond breakage.

EXPERIMENTAL ANALYSIS AND PHYSICAL MODEL INVESTIGATION OF TDDB OF THIN GATE OXIDE

Breakdown character of thin SiO2 is investigated by using substrate hot-carrier injection techniques. Hot-carrier induced thin gate oxide damaged shows different breakdown character compared with the case of conventional F-N tunneling experiments.Good correlation between the calculated electron energy in the oxide and the electric field in the silicon substrate suggests that the difference between hot-electron injection and the F-N tunneling can be explained in terms of the average electron energy in the oxide.Hot holes injection experiments reveal that the life of oxide breakdown is not simply determined by the total number of injected holes.New hot-carrier-induced TDDB (Time-dependent dielectric breakdown)models of thin gate oxide are reported in this paper.

Complementary model for intrinsic time-dependent dielectric breakdown in SiO2 dielectrics

A molecular physics-based complementary model, which includes both field and current, is introduced to help resolve the E versus 1/E-model controversy that has existed for many years as to the true physics behind time-dependent dielectric breakdown (TDDB). It is shown here that either TDDB model can be valid for certain specified field, temperature, and molecular bonding-energy ranges. For bond strengths &amp;lt;3 eV, the bond breakage rate is generally dominated by field-enhanced thermal processes and the E model is valid. For bond strengths &amp;gt;3 eV, the bond breakage must be hole catalyzed by current-induced hole injection and capture. Under these conditions, the TDDB physics is described well by the 1/E model.