Time-constrained Scheduling Research Articles

Large neighborhood search for an aeronautical assembly line time-constrained scheduling problem with multiple modes and a resource leveling objective

Large neighborhood search for an aeronautical assembly line time-constrained scheduling problem with multiple modes and a resource leveling objective

Scheduling Precedence Constrained Tasks for Mobile Applications in Fog Computing

We consider scheduling precedence constrained tasks of a mobile application in a fog computing environment, which faces multiple challenges of precedence constraints, power allocation, and performance-cost tradeoff. Our strategies to handle the three challenges are described as follows. First, in pre-power-allocation algorithms and post-power-allocation algorithms, precedence constraints are handled by the classic list scheduling algorithm and the level-by-level scheduling method respectively. Second, in a pre-power-allocation algorithm (a post-power-allocation algorithm, respectively), a power allocation strategy is determined before (after, respectively) a computation offloading strategy is decided. Third, the performance-cost tradeoff is dealt with by defining the energy-constrained scheduling problem and the time-constrained scheduling problem. That is, between performance and cost, we fix one and minimize the other. The main contributions of the present paper are highlighted as follows. We develop a class of pre-power-allocation algorithms for both energy-constrained and time-constrained scheduling, which are based on the classic list scheduling algorithm and the equal-energy method. We develop a class of post-power-allocation algorithms for both energy-constrained and time-constrained scheduling, which are based on the level-by-level scheduling method and our previously proposed algorithms for independent tasks. We evaluate the proposed algorithms by extensive experiments on mobile applications with randomly generated directed acyclic graphs and identify the most effective and efficient heuristic algorithms. Our research in this paper studies computation offloading in the context of traditional task scheduling while incorporating new and unique features of fog computing into consideration. To the author’s best knowledge, there has been no such and similar study in the current literature.

Energy-Efficient Task Scheduling on Multiple Heterogeneous Computers: Algorithms, Analysis, and Performance Evaluation

The problems of energy-constrained and time-constrained task scheduling on multiple heterogeneous computers are investigated as combinatorial optimization problems. For a given set of independent tasks, our strategy is to find a schedule of the tasks first, and then find a power allocation to the tasks, where the power allocation is performed in such a way that the total task execution time or the total energy consumption is minimized. We are able to find an optimal partition of a given workload and use a modified list scheduling (MLS) algorithm to generate a partition of the set of tasks that is an approximation of the optimal workload partition. Our simulation results demonstrate that when compared with optimal solutions, the MLS algorithm has excellent expected performance in solving the problems of energy-constrained and time-constrained scheduling of independent tasks on multiple heterogeneous computers. For precedence constrained tasks represented by a directed acyclic graph (dag), our level-by-level modified list scheduling (LL-MLS) algorithm schedules tasks level by level (LL) and schedules tasks in the same level by using the MLS algorithm. We are able to solve the problems of optimal energy/time allocation to the levels and optimal workload partition for all levels in a given dag. Our simulation results demonstrate that when compared with optimal solutions, the LL-MLS algorithm has excellent expected performance in solving the problems of energy-constrained and time-constrained scheduling of precedence constrained tasks on multiple heterogeneous computers.

MUS: a novel deadline-constrained scheduling algorithm for Hadoop

Hadoop is a popular framework to process growing volumes of data across clusters of computers, and has achieved great success both in industry and academic researches. Although Hadoop has powerful batch processing capabilities, it can not support the real-time services, such as online payment or monitoring sensor data. These real-time services have strict deadlines in common, where service response after the deadline is considered useless. Current researches on time-constrained scheduling algorithms generally aim at shortening the completion time, rather than guaranteeing the specific latency for the real-time services. In this paper, we study the deadline-constrained scheduling problem on Hadoop, where service requests arrive randomly and no prior information is available. A maximum urgency scheduling MUS algorithm is proposed, and then implemented as a pluggable scheduler on Hadoop. This novel algorithm can be applied in heterogeneous environments with a low computation complexity. Experiments indicate that the MUS algorithm maximises the number of jobs meeting their deadlines while maintains the fairness among different types of jobs.

Approximation Algorithms for Time-Constrained Scheduling on Line Networks

We consider the problem of time-constrained scheduling of packets in a communication network. Each packet has, in addition to its source and its destination, a release time and a deadline. The goal of an algorithm is to maximize the number of packets that arrive to their destinations by their respective deadlines, given the network constraints. We consider the line network, and a setting where each node has a buffer of size B packets (where B can be finite or infinite), and each edge has capacity C≥1. To the best of our knowledge this is the first work to study time-constrained scheduling in a setting when buffers can be of limited size. We give approximation algorithms that achieve expected approximation ratio of O(max {log ∗ n−log ∗ B,1}+max {log ∗Σ−log ∗ C,1}), where n is the length of the line, and Σ is the maximum slack a message can have (the slack is the number of time steps a message can be idle and still arrive within its deadline). A special case of our setting is the setting of buffers of unlimited capacity and edge capacities 1, which has been previously studied by Adler et al. (Theory Comput. Syst. 35(6):599–623, 2002). For this case our results considerably improve upon previous results: We obtain an approximation ratio of $O(\min\{ \log^{*}n, \log^{*}\Sigma, \log^{*} M\})$ (where M is the number of messages in the instance), which is a significant improvement upon the results of Adler et al. who obtained a guarantee of O(min {log n,log Σ,log M}).

Online time-constrained scheduling in linear and ring networks

We consider the problem of scheduling a sequence of packets over a linear network, where every packet has a source and a target, as well as a release time and a deadline by which it must arrive at its target. The model we consider is bufferless, where packets are not allowed to be buffered in nodes along their paths other than at their source. This model applies to optical networks where opto-electronic conversion is costly, and packets mostly travel through bufferless hops. The offline version of this problem was previously studied in M. Adler et al. (2002) [3]. In this paper we study the online version of the problem, where we are required to schedule the packets without knowledge of future packet arrivals. We use competitive analysis to evaluate the performance of our algorithms. We present the first online algorithms for several versions of the problem. For the problem of throughput maximization, where all packets have uniform weights, we give an algorithm with a logarithmic competitive ratio, and present some lower bounds. For other weight functions, we show algorithms that achieve optimal competitive ratios.

A genetic algorithm for the design space exploration of datapaths during high-level synthesis

High-level synthesis is comprised of interdependent tasks such as scheduling, allocation, and module selection. For today's very large-scale integration (VLSI) designs, the cost of solving the combined scheduling, allocation, and module selection problem by exhaustive search is prohibitive. However, to meet design objectives, an extensive design space exploration is often critical to obtaining superior designs. We present a framework for efficient design space exploration during high-level synthesis of datapaths for data-dominated applications. The framework uses a genetic algorithm (GA) to concurrently perform scheduling and allocation with the aim of finding schedules and module combinations that lead to superior designs while considering user-specified latency and area constraints. The GA uses a multichromosome representation to encode datapath schedules and module allocations and efficient heuristics to minimize functional and storage area costs, while minimizing circuit latencies. The framework provides the flexibility to perform resource-constrained scheduling, time-constrained scheduling, or a combination of the two, using a simple and fast list-scheduling technique. A graded penalty function is used as an objective function in evaluating the quality of designs to enable the GA to quickly reach areas of the search space where designs meeting user specified criteria are most likely to be found. Since GAs are population-based search heuristics, a unique feature of our framework is its ability to offer a large number of alternative datapath designs, all of which meet design specifications but differ in module, register, and interconnect configurations. Many experiments on well-known benchmarks show the effectiveness of our approach.

Time-constrained scheduling of large pipelined datapaths

This paper addresses the most crucial optimization problem of high-level synthesis: scheduling. A formal framework is described that was tailored specifically for the definition and investigation of the time-constrained scheduling problem of pipelined datapaths. Theoretical results are presented on the complexity of the problem. Moreover, two new heuristic algorithms are introduced. The first one is a genetic algorithm, which, unlike previous approaches, searches the space of schedulings directly. The second algorithm realizes a heuristic search using constraint logic programming methods. The performance of the proposed algorithms has been evaluated on a set of benchmarks and compared to previous approaches.

Conversion of coloring algorithms into maximum weight independent set algorithms

A general technique for converting approximation algorithms for the vertex coloring problem in a class of graphs into approximation algorithms for the maximum weight independent set problem (MWIS) in the same class of graphs is presented. The technique consists of solving an LP-relaxation of the MWIS problem with certain clique inequalities, constructing an instance of the vertex coloring problem from the LP solution, applying the coloring algorithm to this instance, and selecting the best resulting color class as the MWIS solution. The approximation ratio obtained is the product of the approximation ratio with which the LP formulation can be solved (usually equal to one) and the approximation ratio of the coloring algorithm with respect to the size of the largest relevant clique. Applying this technique, the best known approximation algorithms are obtained for the maximum weight edge-disjoint paths problem in bidirected trees and in bidirected two-dimensional meshes with row–column routing, and for time-constrained scheduling of weighted packets in the same topologies. These problems are also proved to be MAX SNP-hard.

Time-Constrained Scheduling and Module Allocation for On-Line Testability in Pipelined Data Paths

Abstract This paper presents an on-line testable-pipelined data path synthesis with the goal of minimizing testing time. An independent time-constrained scheduling with a module allocation algorithm for a pipelined data path is proposed. The algorithm takes any behavioral description represented as a data flow graph as input and generates a pipelined data path. The pipelined data path is composed of resources such as modules, registers, and multiplexers. Our on-line testing methodology applies to modules where multi type operations are assigned. The test is performed on each type of operation assigned to a module. The testing time is reduced by minimizing the overall number of types of operations assigned to modules. Thus, the objective is to minimize the overall number of types of operations assigned to all modules by performing pipelined data path synthesis. Experimental results confirm there can be some improvement in minimizing the overall number of types of operations assigned to all modules.

Time-Constrained Scheduling of Weighted Packets on Trees and Meshes

The time-constrained packet routing problem is to schedule a set of packets to be transmitted through a multinode network, where every packet has a source and a destination (as in traditional packet routing problems) as well as a release time and a deadline. The objective is to schedule the maximum number of packets subject to deadline constraints. This problem is studied in [1], where it is shown that the problem is NP-Complete even when the underlying topology is a linear array. Approximation algorithms are also provided in [1] for the linear array and the unidirectional ring for both the case where packets may be buffered in transit and the case where they may not be.

Scheduling of Pipelined Data Paths for On-line Testability

Abstract This paper presents a time-constrained scheduling of a pipelined data path with the perspective of improving on-line testability. The testability is incorporated at the scheduling phase of the synthesis. Being a presynthesis method, the approach minimizes the area overhead. Operations of the same type are assigned to resources called functional units (FU). The on-line testing is carried out by capturing selective input and output variables of a circuit under test (CUT) in time frames called passes. The captured variables are shifted out to an external testing unit for verification. Each FU of the CUT is tested at least once in each pass. Minimizing the number of variables needed to test all FUs reduces the testing time. Thus, the scheduling is performed with the objective of improving on-line testability by minimizing the number of FUs and the number of variables needed to test all FUs. Promising results are obtained on benchmark examples.

A scheduling method with search space reduction

In this paper, we propose a time-constrained scheduling approach to minimize resource cost. Most previous approaches cannot estimate resource costs completely in the initial scheduling process, because most operations have not been assigned yet. Therefore, our approach eliminates the operation and control step pair with the maximum resource cost. In order to minimize total resource cost, we also estimate the resource cost of functional units, registers, and buses based on the distribution of operations. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 82(1): 34–42, 1999

A greedy randomised search heuristic for time-constrained vehicle scheduling and the incorporation of a learning strategy

A greedy randomised search heuristic for time-constrained vehicle scheduling and the incorporation of a learning strategy

A greedy randomised search heuristic for time-constrained vehicle scheduling and the incorporation of a learning strategy

In this paper, a greedy randomised heuristic is applied to a complex vehicle-scheduling problem with tight time windows and additional constraints. Two forms of adaptive search are identified, which are referred to as local and global adaptation. In both cases, the calculation of the greedy function is modified by an amount which measures heuristically the quality of the partial solution that is obtained when a decision is made. One use of global adaptation is an approach which is referred to as a learning strategy since it involves an attempt to learn from previous mistakes by an appropriate updating of the greedy function from one run of the heuristic to the next. Such a learning strategy forms the main focus of this paper. Experimental results show that it is potentially a powerful heuristic device, since it greatly enhanced the effectiveness of those methods that had previously been applied to this problem; that is, a greedy randomized heuristic which also incorporated a look-ahead strategy and a version of the well-known savings method. It is suggested that learning strategies of the general type introduced in this paper have potential for application to other combinatorial optimisation problems.

A Greedy Randomised Search Heuristic for Time-Constrained Vehicle Scheduling and the Incorporation of a Learning Strategy

A Greedy Randomised Search Heuristic for Time-Constrained Vehicle Scheduling and the Incorporation of a Learning Strategy

A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis

In this paper we propose a generalized technique to count the required number of registers in a schedule which supports overlapped scheduling and can be applied to the case where a general digit-serial data format is used. This technique is integrated into an integer linear programming (ILP) model for time-constrained scheduling. In the ILP model, appropriate processors of certain data formats are chosen from a library of processors and data format converters are automatically inserted between processors of different data formats if necessary. Then the required number of registers for each data format is evaluated correctly by the proposed technique. Hence an optimal architecture for a given digital signal processing algorithm is synthesized where the cost of registers as well as the cost of processors and data format converters are minimized. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8% savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.

Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors

Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip. A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability and fault-tolerance are making on-chip fault-tolerance mandatory. On-chip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in life-critical systems should be secured against all faults. While fault-security can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive fault-secure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead.

A formal approach to the scheduling problem in high level synthesis

An integer linear programming (ILP) model for the scheduling problem in high-level synthesis is presented. In addition to time-constrained scheduling and resource-constrained scheduling, a scheduling problem called feasible scheduling, which provides a paradigm for exploring the solution space, is constructed. Extensive consideration is given to the following applications: scheduling with chaining, multicycle operations by nonpipelined function units, and multicycle operations by pipelined function units; functional pipelining; loop folding; mutually exclusive operations; scheduling under bus constraint; and minimizing lifetimes of variables. The complexity of the number of variables in the formulation is O(s*n) where s and n are the number of control steps and operations, respectively. Since the as soon as possible (ASAP), as late as possible (ALAP), and list scheduling techniques are used to reduce the solution space, the formulation becomes very efficient. A solution to a practical problem, such as the fifth-order filter, can be found optimally in a few seconds. >

Maximizing throughput in some simple time-constrained scheduling situations

This contribution focuses on some interesting phenomena occurring in scheduling capacity constrained resources in time-constrained situations. The scheduling situations considered form part of a simulation game developed to assist in teaching the scheduling philosophy of Optimized Production Technology (OPT) to production managers. It is shown that under certain conditions on set-up and processing times, advanced examples may be constructed combining three of the four complicating conditions mentioned m the OPT-literature. In addition, some interesting properties of process batches yielding a maximum throughput in such cases is considered.