Ti Silicide Research Articles

A novel self-aligned T-shaped gate process for deep submicron Si MOSFET's fabrication

T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure.

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm CMOS

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Real-Time Observation of Ti Silicide Epitaxial Islands Growth with the Photoelectron Emission Microscopy

AbstractThe formation of nanoscale Ti silicide islands was observed by Photo-electron emission microscopy (PEEM). The islands were prepared by deposition of an ultrathin Ti (3–12ML) on Si(001) at room temperature and at an elevated temperature of 950°C. The island formation was initiated by in situ annealing to 1150° C. It was observed that initially Ti silicide islands form while longer annealing indicates some islands move and coalesce with other islands. Most of the islands are similar in size and have relatively uniform separation. Also, it was shown that for continued Ti deposition at a temperature of 950°C, the density of islands did not increase. However, islands grew together when their perimeter lines touch each other. The results are described in terms of island growth processes of coalescence and ripening.

A Novel Low Temperature Self-Aligned Ti Silicide Technology for Sub-0.18 μm Cmos Devices

ABSTRACTA novel low temperature self-aligned Ti silicidation with Ge+ pre-amorphization implant (PAI) is presented. Compared to conventional high temperature PAM silicidation, the advantages of Ti salicidation at temperatures below the recrystallization of a pre-amorphized layer are: (1) C49 TiSi2 silicide formation occurs only in the pre-amorphized layer so that the silicide depth can be well controlled, forming a very sharp interface between the silicide and the Si substrate; (2) Ti just reacts with the amorphous layer, avoiding the so-called bridging issue in which the silicide grows laterally over the isolation or spacer; (3) the effects of metal thickness and substrate doping on silicide formation are suppressed.

A Novel Low Temperature Self-Aligned Ti Silicide Technology for Sub-0.18 μm CMOS Devices

ABSTRACTA novel low temperature self-aligned Ti silicidation with Ge+ pre-amorphization implant (PAI) is presented. Compared to conventional high temperature PAI silicidation, the advantages of Ti salicidation at temperatures below the recrystallization of a pre-amorphized layer are: (1) C49 TiSi2 silicide formation occurs only in the pre-amorphized layer so that the silicide depth can be well controlled, forming a very sharp interface between the silicide and the Si substrate; (2) Ti just reacts with the amorphous layer, avoiding the so-called bridging issue in which the silicide grows laterally over the isolation or spacer; (3) the effects of metal thickness and substrate doping on silicide formation are suppressed.

The effect of precleaning treatments on the formation of Ti silicide

In this work, the effect of the wafer precleaning procedure for low resistance titanium silicide film growth was investigated. This involved Ar sputtering treatment, APM cleaning, HPM cleaning and dilute-HF dipping. The low resistance TiSi 2 film formation was realized by a wet precleaning to remove oxide from the Si surface. The higher sheet resistance of TiSi 2 film treated by Ar dry cleaning was explained by the thinner film thickness and the interface roughness. Knock-on contaminants trapped in an interfacial amorphous Si layer were formed in the remaining native oxide during Ar dry cleaning. Although a small amount of oxygen at the interface had little influence on the silicidation reaction, knocked-on oxygen and nitrogen inhibited the silicidation reaction.

Reaction of Ti with WSi2

Reactions between Ti and WSi2 have been studied between 400 and 800 °C. Reactions at the Ti–WSi2 interface begin at 600 °C, with the formation of TiSi. The TiSi is converted to TiSi2 at 800 °C. The formation temperatures for TiSi and TiSi2 are higher than those observed for Ti on Si, presumably because the Si supply is limited by relatively slow diffusion of Si through WSi2. At 700 °C, localized formation of Ti silicide is also observed below the WSi2, due to Ti diffusion through grain boundaries in the WSi2. These results suggest that post-metallization anneals of Ti on WSi2 polycide structures should be kept below 700 °C to avoid device degradation.

Thermodynamic assessment for shock wave synthesis of transition metal silicides

The initial state of the porous elemental powders is taken at 298°K. The final state is the fully reacted powders at the adiabatic temperature, T_(ad). Energy is input by the shock wave E_(shock) and by the negative enthalpy of formation ΔH_f of the silicide, E_(in) = E_(shock) – ΔH_f. The adiabatic process takes place on a closed system, and therefore T_(ad) depends only on the end points and not on the path of the process. We may therefore assume full reaction takes place first, followed by the input of the shock energy. Three regimes for T_(ad) are considered, where the heat of fusion of the silicide is given by ΔH_m. Define a function F(T_(upper)) as the integral of c_pdT from 298°K to temperature T_(upper), where c_p is the specific heat of the silicide given by c_p = A+ 10^(-3)BT+ 10^5CT^(-2) with constants A, B, and C. The input energy is converted to heat, and T_(ad) is obtained from: Regime I: T_(ad) < T_m, v = 0, and E_(in) = F(T_(ad)) where T_m is the silicide melting temperature, and v is the fraction of silicide melted. Regime II: T_(ad) = T_m, 0 ≤ v ≤ 1, for F(T_m) ≤ E_(in) ≤ F(T_m) +ΔH_m, and v = [E_(in) - F(T_m)]/C_(pl) where c_(pl) is the specif1c heat of the liquid silicide. Regime III: T_(ad) > T_m, v = 1, for E_(in) > F(T_m) + ΔH_m, and T_(ad) = T_m + [E_(in) - F(T_m) – ΔH_m]/c_(pl). The pressure dependence of the silicide melting points has not been determined and the zero pressure melting points were used in the calculations. (The silicon melting point decreases by 54°K/GPa (2), while that of the metals increases (3).) An iterative method of solution was employed to obtain T_(ad) in regime I. Calculations were made for the disilicides and 5:3 silicides of Cr, Mo, Nb, Re, Ta, Ti, V, W, and Zr. The silicide property values employed by Bhaduri et al. (1) were used, with the exception of ΔH_f values for Ti silicides (-88.48 J/mol for TiSi_2 and -288.8 J/mol for Ti_5Si_3) which were obtained from Ref. 4. Table I lists T_(ad) values at zero shock energy calculated here and in Ref. 1 for the 1:2 and 5:3 silicides. Table II gives calculated values of the shock energy required to reach the silicide melting point, the shock energy to melt the silicide, and the silicide melting point. Calculated values of Tad vs. shock energy are presented in Figs. 1 and 2.

Surface processes occurring on TiSi2 and CoSi2 in fluorine-based plasmas. Reactive ion etching in CF4/CHF3 plasmas

The kinetics of TiSi2 and CoSi2 etching in CF4/CHF3 plasmas are studied. X-ray photoelectron spectroscope studies show that after the reactive ion etching (RIE) etching of TiSi2 and CoSi2 with different gas composition, complex protective films, containing both CFx polymers and metal fluorides, are formed. The relative amount of metal fluoride and polymer depends on the gas composition. A phenomenological model describing the RIE of the metal silicides in the carbon–fluoride plasmas is established. It is shown that in the case of TiSi2, selective etching of SiO2 can be obtained by increasing the polymer precursor radical concentration in the plasma. Effective ways for the removal of the post-dry-etch residues from the TiSi2 and CoSi2 surfaces have been developed. It is shown that the use of a complex cleaning procedure, including both the SPM (H2SO4:H2O2=4:1) and O2–plasma treatments, provides practically clean surfaces of both the Ti and Co silicides without the metal fluorides and polymers.

Structural investigation of thermally nitrided amorphous Ti silicide

Thermal nitridation of thin amorphous Ti-silicide films is studied. The use of hydrazine gas enables the nitridation at 500 °C, well below the nucleation temperature of Ti silicide. Transmission electron microscopy reveals that these TiSiN fims have amorphous structures, which are shown to be stable up to 750 °C. X-ray photoelectron spectroscopy indicates the simultaneous formation of Ti–N and Si–N bonds. This is consistent with the Ti–Si–N ternary phase diagram. Further, the presence of this nitrided film between Al and Si retards the interfacial reaction up to an annealing temperature of 550 °C near the eutectic point (577 °C) of an Al–Si system.

Anomalous Junction Leakage Behavior of Ti Self Aligned Silicide Contacts on Ultra-Shallow Junctions

An anomalous junction leakage is observed in Ti self aligned silicide (Ti-SALICIDE) contacts on ultra-shallow junctions less than 0.1 µ m. After annealing at around 460° C for 30 min, the leakage current increases considerably for n+/p junctions and decreases slightly for p+/n junctions. At a reverse bias of 1 V, the activation energies of the leakage current for n+/p junctions and p+/n junctions annealed at 460° C for 30 min are 0.16 eV and 0.97 eV, respectively. The very small activation energy for the n+/p junction can be explained by a tunneling current. The results of secondary-ion mass spectroscopy (SIMS), transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDX) analyses indicate that a considerable amount of Ti diffuses into n+-Si at around 460° C. However, only a small amount of Ti diffuses into p+-Si. This anomalous junction leakage can be explained in terms of tunneling assisted by traps due to the diffused Ti. These low temperature phenomena are thought to represent the process in the early stage of Ti silicidation.

Rapid Thermal Process for Enhancement of Collimated Titanium Nitride Barriers

A rapid thermal processing (RTP) method to improve the barrier properties of collimated titanium nitride (TiN) was studied. The RTP for the collimated TiN shows a significantly improved diffusion barrier property with reduced electrical contact resistance compared to a conventional furnace annealing process. Aluminum planarization was performed on subhalf micron contacts with various TiN barrier processes to examine electrical properties. When RTP is used collimated TiN of much smaller thickness than the furnace‐annealed collimated TiN shows reliable electrical contact properties without junction leakage failure at subhalf micron contacts. When simultaneous in situ RTP for Ti silicidation and stuffing is performed, we obtain greatly improved p+ contact resistance. This is due to the phase transformation of Ti‐Si amorphous layer to crystalline at Si/barrier interface, as observed by cross‐sectional transmission electron microscope.

Ohmic contact to GaN grown by MOCVD

AbstractWe investigated the electrical properties and interfacial reactions of the Si/Ti based ohmic contacts to n-GaN grown by metal organic chemical vapor deposition and the electrical properties were related to the material reactions. The perfect ohmic characteristics were obtained after annealing at 700 °C for 3 min under N2 ambient, and Ti silicide was formed in Ti-Si based contact systems. The lowest value for the specific contact resistance of 3.86×10-6 Ωcm2 was obtained for Au(1000 Å)/Ni(400 Å)/Ti(400 Å)/Si(1460 Å)/Ti(150 Å) after annealing at 900 °C for 3min. It could be concluded from the material analyses that the ohmic characteristics of Ti-Si based contact systems were due to the low barrier height by the formation of Ti silicides with a low work function

Effect of Impurities on Growth of Ti Silicides in Bulk Ti/Si Diffusion Couple

Reaction diffusion and the Kirkendall effect in Ti-Si binary system have been studied by using sandwich-type bulk diffusion couples consisting of 99.99% Ti, 99.9999% Ti plates and a oriented Si wafer. The results have been compared with our previous one obtained by using 99.99% Ti/Si and 99.5% Ti/Si couples. The faster growth of TiSi 2 formed in these Ti/Si diffusion couples, the higher the purity of titanium. To identify the element which slows down the growth rate of TiSi 2 , the effects of oxygen, nitrogen, carbon and iron were studied by adding oxygen and nitrogen into 99.9999% Ti or by depositing carbon and iron on the Ti surface. It has been clarified that iron atoms slow down the growth of TiSi 2 . Silicon atoms diffuse 50 to 100 times faster than titanium atoms in TiSi 2 . Iron affects the diffusivity of Si more effectively than that of Ti. On the basis of these results the role of iron in the Ti/Si bulk reaction diffusion couple has been discussed by taking into account a possibility of diffusion barrier effect or grain boundary diffusion.

Materials aspects of Ti and Co silicidation of narrow polysilicon lines

The scalability of Ti and Co self-aligned silicide processes to deep-submicrometer technologies is determined by the fundamental materials aspects controlling phase formation and evolution. The kinetics of the high resistivity phase to low resistivity phase transformation (TiSi 2 C49 to C54 transformation for Ti, and CoSi to CoSi 2 transformation for Co) were studied for films on deep-submicrometer n + gates. For TiSi 2, results of a detailed Johnson-Mehl-Avrami analysis show that activation energies for the transformation increase with decreasing film thickness in the 28–64 nm range and are insensitive to linewidth in the 0.26-0.8 μm range, while transformation times increase as the linewidth or film thickness decreases. For Co, the transformation is diffusion limited, whih the square of CoSi 2 film thickness depending linearly on time. The transformation rate is also observed to be linewidth dependent, while the activation energy is quite insensitive to linewidth. The Co silicide phase tranformation proceeds faster than the Ti silicide phase transformation at low temperatures, resulting in a range of process parameters for which no linewidth dependence is observed for Co silicide and a strong linewidth dependence is observed for Ti silicide owing to incomplete phase transformation of the narrowest lines.

TiSi 2 phase transformation characteristics on narrow devices

Accurate prediction of TiSi 2 transformation requires test structures with small silicided surface areas. To evaluate the area dependence of the C49 to C54 transformation, a new monitor was developed with minimal silicide surface area. Small area structures were found to exhibit a bimodal resistance distribution that was nearly insensitive to process transformation conditions. Starvation for C54 nucleation sites resulted in a high frequency of non-transformation even at high annealing temperatures. Transmission electron microscopy analysis showed that the Ti silicide in these structures is either C49 or C54 phase, with little or no mixed phases present. A cooperative C54 nucleation mechanism is proposed to explain this phenomena. The presence of small quantities of a molybdenum impurity such as molybdenum during silicide formation has been found to increase the availability of C54 forming nuclei by two orders to magnitude. The molybdenum acts as a catalyst and does not require interface mixing or the creation of an amorphous Si layer to enhance nucleation. The addition of molybdenum has been demonstrated to eliminate the bimodal resistance distribution.

PZT capacitor with Ir/IrO2/Ir electrode fabricated by RTA

Abstract PZT capacitor with direct contact between Si substrate and bottom electrode of the capacitor was obtained with Ir/IrO2/Ir/Ti electrode, by crystallizing sol-gel PZT thin film using RTA (650°CC 30 sec.). Contact resistance for hole diameter of 0.72 μm was 19 Ω. It was observed by cross-sectional TEM that Ti silicide was formed at the interface, but there was not oxygen diffusion from PZT thin film. Fatigue property of the PZT thin film was improved by RTA compared with furnace annealed film (600°CC 60 min.). The absolute value of the remnant polarization was 13 μC/cm2 for both films, but it did not degrade until 108 cycles of switching for the film by RTA, while it degraded before 105 cycles for furnace annealed film.

Surface and interface studies of titanium silicide formation

Secondary ion mass spectrometry (SIMS), Rutherford backscattering spectroscopy (RBS) and X-ray photoelectron spectroscopy (XPS) are used to investigate Ti silicide formation mechanisms on a series of Ti on Si thin-films annealed in ultrahigh vacuum (UHV) at different temperatures and durations. The competition between oxygen diffusion and the silicide formation reaction (the so-called ‘snowplough’ effect) is observed directly, as well as a TiSiO layer. The results from these controlled experiments are compared with those from Ti-silicide films formed under rapid thermal annealing (RTA) conditions in a production furnace, with and without a TiW barrier layer. The TiW layer is shown to act as an effective barrier to silicon and oxygen out-diffusion, as well as the incorporation of ambient gases.

Metal Microstructures in Advanced CMOS Devices

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.