Through Silicon Via Research Articles

Atomic-scale insights into the microstructure and interface evolution mechanism of copper/tantalum nanofilms during ultra-precision grinding

The copper (Cu)/tantalum (Ta) nanofilms are the vital component in the through silicon via (TSV) wafer. However, the current lack of research on the ultra-precision machining of Cu/Ta nanofilms limits the development of TSV-based 3D integration technologies. In this work, molecular dynamics simulations are conducted to reveal the microstructure and interface evolution mechanism of Cu/Ta nanofilms during nano-grinding under various grinding depths. The results show that the material removal mode differs between the Cu and Ta layers, and the thickness of the subsurface damage layer of the Cu layer is greater than that of the Ta layer. The Cu/Ta interface is well stabilized, and small amounts of micro-defects appear only at larger grinding depths after grinding. The lattice mismatch of the constituent layers and the hindering role by the interface lead to stress concentration at the interface, and it is more obvious with increasing grinding depth. Nevertheless, there is a significant stress release after grinding. Our computations indicate that the competition between the evolution of interfacial structures and discrepancies in the physical properties of constituent layers leads to an increase in grinding forces at the interface. Furthermore, the heat transfer is obstructed by the Cu/Ta interface. This study provides valuable insights into the grinding mechanisms of Cu/Ta nanofilms, which is conducive to further improving the manufacturing process of the TSV wafer and enhancing the performance of microelectronic devices.

Multi-physical field coupling effect in micro pin-fin channel cooling with coaxial-like through-silicon via (TSV) for three-dimensional integrated chip (3D-IC)

Multi-physical field coupling effect in micro pin-fin channel cooling with coaxial-like through-silicon via (TSV) for three-dimensional integrated chip (3D-IC)

Microfabrication Technologies for Nanoinvasive and High-Resolution Magnetic Neuromodulation.

The increasing demand for precise neuromodulation necessitates advancements in techniques to achieve higher spatial resolution. Magnetic stimulation, offering low signal attenuation and minimal tissue damage, plays a significant role in neuromodulation. Conventional transcranial magnetic stimulation (TMS), though noninvasive, lacks the spatial resolution and neuron selectivity required for spatially precise neuromodulation. To address these limitations, the next generation of magnetic neurostimulation technologies aims to achieve submillimeter-resolution and selective neuromodulation with high temporal resolution. Invasive and nanoinvasive magnetic neurostimulation are two next-generation approaches: invasive methods use implantable microcoils, while nanoinvasive methods use magnetic nanoparticles (MNPs) to achieve high spatial and temporal resolution of magnetic neuromodulation. This review will introduce the working principles, technical details, coil designs, and potential future developments of these approaches from an engineering perspective. Furthermore, the review will discuss state-of-the-art microfabrication in depth due to its irreplaceable role in realizing next-generation magnetic neuromodulation. In addition to reviewing magnetic neuromodulation, this review will cover through-silicon vias (TSV), surface micromachining, photolithography, direct writing, and other fabrication technologies, supported by case studies, providing a framework for the integration of magnetic neuromodulation and microelectronics technologies.

Discharge characteristics of silicon-based DC Helium microplasmas: comparison between Through Silicon Via and closed cavity type micro-reactors

Abstract This paper explores the microfabrication process of plasma reactors, from the production of micro-reactors to the addition of Through Silicon Vias (TSV) using proprietary etching techniques and on site cleanroom facilities. The investigation focuses on both newly fabricated closed and open-cavity Micro-Hollow Cathode Discharge (MHCD) reactors, with particular emphasis on electrical and optical diagnostics to characterize their plasma properties. All experiments, including those on closed-cavity reactors, were specifically conducted for this study under identical conditions to ensure a rigorous comparison between reactor types. When electrical diagnostics were carried out in helium at various pressures, interesting phenomena such as the evolution of voltage breakdown were observed. These diagnostics also provided new insights into the impact of surface electrode and overall geometry properties and pressure on reactor performance. 
Additional investigation into instability mechanisms revealed self-pulsing oscillations, with different reactor types having different oscillation amplitudes for similar operating conditions. Optical emission spectroscopy (OES) emerged as a strong tool for spatial plasma analysis, revealing consistent gas temperature distributions across reactor diameters. The Inglis-Teller series provided an estimate of the upper limit of electron density, while the Stark broadening analysis of Hα offered valuable insights into electron density variations, particularly in the self-pulsing regime.

Electrical–Thermal Co-Analysis of Through-Silicon Vias (TSVs) Integrated Within Micropin-Fin Heatsink for 3-D Heterogeneous Integration (HI)

Electrical–Thermal Co-Analysis of Through-Silicon Vias (TSVs) Integrated Within Micropin-Fin Heatsink for 3-D Heterogeneous Integration (HI)

Atomistic simulations of the thinning process of tantalum/copper heterostructure in wafer containing through silicon via

Through silicon via (TSV) interconnect structure plays an essential role in high-density 3-D integration. The tantalum (Ta)/copper (Cu) heterointerface is one of the significant interfaces in the wafer containing TSV. Molecular dynamics simulations are utilized to study the interface evolution and thinning mechanism of Ta/Cu heterostructure at different grinding depths during the thinning process. It is found that atomic diffusion, amorphization, phase transition, and micro-defects are typical characteristics of interfacial evolution, which become more pronounced at deeper grinding depths. The extrusion of the hard Ta layer on the soft Cu layer leads to an early appearance of interface defects, including dislocations and stacking faults. It is revealed that the large lattice mismatch of the constituent layers and obstruction of the heterointerface result in obvious stress concentration. The reduced tangential and normal forces at the interface are ascribed to atomic structure evolution and intrinsic properties of the heterostructure. Additionally, the heterointerface can hinder heat conduction between the Ta and Cu layers. These findings can provide valuable guidance for the manufacture of the wafer containing TSV.

Moore's Law Scaling and Chemical Mechanical Planarization (CMP)

Since the invention of the first integrated circuit in 1958, chemistry and materials have played a critical role in semiconductor process technologies, which has led to an exponential growth of transistors packed into circuits. Decades ago, Gordon Moore posited there would be a doubling of components every two years (revised from his original doubling every one-year prediction). This observation became known as Moore’s law.As Denard scaling took on more complexity, the number of new materials used to build semiconductors increased at a torrid pace. The number of elements in the periodic table, used to fabricate devices, increased roughly five-fold from the 1980’s to the 2000’s.In the earlier years, lithography, etch, thin films, implant, and diffusion were foundational technologies used to fabricate a silicon wafer into hundreds of microchips. In the late 1980’s a new technology Chemical Mechanical Planarization (CMP) was invented. It was developed out of necessity to reduce topography, critical for lithography’s depth of focus requirements. Without this key invention, patterning and building layer upon layer from front end transistors to back-end interconnects would not have been possible.Intel implemented CMP into manufacturing in the early 1990’s on the 0.8 micron technology node which manufactured the 486 microprocessor. CMP was required to planarize dielectric oxide used to insulate the aluminum metal interconnects. Since then, the number of CMP applications over the last three decades has exploded, enabling the scaling of Moore’s Law.CMP is not only used to improve lithography depth of focus. CMP also enables a method of metal interconnect and contact formation called damascene. Planarization is used to create dielectric isolation trenches, discrete plugs for insulation, aid advanced patterning architectures, build through silicon vias (TSVs), and enable complex wafer and chip bonding for die-to-die interconnects for disaggregated products.Transistor scaling alone is no longer sufficient to meet device performance, power, and cost requirements. Complex material and architectural changes are required. And novel CMP applications continue to be added at each new technology node. This author will make an argument that CMP is critical to push scaling and enable future process nodes. Figure 1

Atomic-Scale Investigation of Electromigration Behavior in Cu-to-Cu Joints at High Current Density

Three-dimensional integrated circuit (3D IC) packaging offers significant advantages, such as enhanced computational efficiency through greater integration and shorter interconnection distances. The effective interconnection of layers, particularly through redistribution layer (RDL) technology, is crucial for the successful operation of 3D ICs. While copper remains the preferred material for interconnections, often in conjunction with through-silicon via (TSV) technology for chip-to-chip links, the shrinking dimensions of components present challenges. In particular, the reduction in size may lead to elevated current densities in individual joints, giving rise to issues like electromigration (EM) and potential failure. EM-induced atomic migration may lead to the formation of voids in the interconnection. The accumulation of voids to a critical point may result in an open circuit in the joints, significantly impacting the conductor's reliability. This work delves into the micro-scale aspects of these challenges, complementing previous macroscopic investigations. We aim to elucidate the behavioral mechanisms through atomic-scale observations, employing an in-situ high-resolution transmission electron microscope (in-situ HRTEM) to observe atomic-scale images of EM. The insights gained from this work not only contribute to the academic understanding of industry challenges but hold potential applications in real-world manufacturing processes. Fig. 1. (a) Schematic diagram of TEM sample preparation. (b) Cross-sectional HRTEM image of copper bonding. (c, d) TEM images showing voids expansion at bonding interface. Figure 1

Synergistic effect of CTA+ and Br- on defect-free TSV filling by Cu electrodeposition

Suppressing additives for Cu electrodeposition play a critical role in inducing bottom-up filling in micrometer-scale features such as through-silicon vias (TSVs). This study explores the adsorptive behaviors of cetyltrimethylammonium cation (CTA+) and bromide ion (Br-) and their application to defect-free TSV filling. Electrochemical analyses reveal that both CTA+ and Br- suppress Cu electrodeposition, with only CTA+ exhibiting negative differential resistance (NDR) behavior. The addition of Br- to CTA+ enhances the suppression effect while maintaining the NDR behavior of CTA+. TSV filling experiments demonstrate that the NDR behavior of the CTA+ and Br- combination induces the passive-active transition on the sidewalls of TSVs, which is essential for Cu bottom-up filling. The effects of CTA+ and Br- concentrations on the passive-active transition are also investigated, showing that CTA+ determines the height at which the passive-active transition occurs, while Br- enhances suppression to inhibit Cu growth on the sidewalls in the active region. Based on these behaviors, the optimal CTA+-Br- combination leads to successful bottom-up filling in TSVs. The mechanisms of TSV filling with CTA+ and Br- are suggested based on electrochemical analyses and gap-filling results. The active region at the TSV bottom, formed via selective breakdown of suppressing adsorbates, is filled while effectively inhibiting Cu deposition on the sidewalls, followed by filling the remaining portion of TSVs with vertical Cu growth.

In vivo optogenetics using a Utah Optrode Array with enhanced light output and spatial selectivity

Objective.Optogenetics allows the manipulation of neural circuitsin vivowith high spatial and temporal precision. However, combining this precision with control over a significant portion of the brain is technologically challenging (especially in larger animal models).Approach.Here, we have developed, optimised, and testedin vivo, the Utah Optrode Array (UOA), an electrically addressable array of optical needles and interstitial sites illuminated by 181μLEDs and used to optogenetically stimulate the brain. The device is specifically designed for non-human primate studies.Main results.Thinning the combinedμLED and needle backplane of the device from 300μm to 230μm improved the efficiency of light delivery to tissue by 80%, allowing lowerμLED drive currents, which improved power management and thermal performance. The spatial selectivity of each site was also improved by integrating an optical interposer to reduce stray light emission. These improvements were achieved using an innovative fabrication method to create an anodically bonded glass/silicon substrate with through-silicon vias etched, forming an optical interposer. Optical modelling was used to demonstrate that the tip structure of the device had a major influence on the illumination pattern. The thermal performance was evaluated through a combination of modelling and experiment, in order to ensure that cortical tissue temperatures did not rise by more than 1 °C. The device was testedin vivoin the visual cortex of macaque expressing ChR2-tdTomato in cortical neurons.Significance.It was shown that the UOA produced the strongest optogenetic response in the region surrounding the needle tips, and that the extent of the optogenetic response matched the predicted illumination profile based on optical modelling-demonstrating the improved spatial selectivity resulting from the optical interposer approach. Furthermore, different needle illumination sites generated different patterns of low-frequency potential activity.

Reliability Simulation Analysis of TSV Structure in Silicon Interposer under Temperature Cycling.

As semiconductor integration scales expand and chip sizes shrink, Through Silicon Via (TSV) technology advances towards smaller diameters and higher aspect ratios, posing significant challenges in thermo-mechanical reliability, particularly within interposer substrates where mismatched coefficients of thermal expansion exacerbate issues. This study conducts a thermo-mechanical analysis of TSV structures within multi-layered complex interposers, and analyzes the thermal stress behavior and reliability under variable temperature conditions (-55 °C to 85 °C), taking into account the typical electroplating defects within the copper pillars in TSVs. Initially, an overall model is established to determine the critical TSV locations. Sub-model analysis is then employed to investigate the stress and deformation of the most critical TSV, enabling the calculation of the temperature cycle life accordingly. Results indicate that the most critical TSV resides centrally within the model, exhibiting the highest equivalent stress. During the temperature cycling process, the maximum deformation experiences approximately periodic variations, while the maximum equivalent stress undergoes continuous accumulation and gradually diminishes. Its peak occurs at the contact interface corner between the TSV and Redistribution Layer (RDL). The estimated life of the critical point is 3.1708 × 105 cycles. Furthermore, it is observed that electroplating defect b alleviates thermal stress within TSVs during temperature cycling. This study provides insights into TSV thermal behavior and reliability, which are crucial for optimizing the design and manufacturing processes of advanced semiconductor packaging.

Fast in-line failure analysis of sub-micron-sized cracks in 3D interconnect technologies utilizing acoustic interferometry

More than Moore technology is driving semiconductor devices towards higher complexity and further miniaturization. Device miniaturization strongly impacts failure analysis (FA), since it triggers the need for non-destructive approaches with high resolution in combination with cost and time efficient execution. Conventional scanning acoustic microscopy (SAM) is an indispensable tool for failure analysis in the semiconductor industry, however resolution and penetration capabilities are strongly limited by the transducer frequency. In this work, we conduct an acoustic interferometry approach, based on a SAM-setup utilizing 100 MHz lenses and enabling not only sufficient penetration depth but also high resolution for efficient in-line FA of Through Silicon Vias (TSVs). Accompanied elastodynamic finite integration technique-based simulations, provide an in-depth understanding concerning the acoustic wave excitation and propagation. We show that the controlled excitation of surface acoustic waves extends the contingency towards the detection of nm-sized cracks, an essential accomplishment for modern FA of 3D-integration technologies.

A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration

Three-dimensional integration circuit (3D IC) offers significant benefits in terms of performance and cost. Existing research in through-silicon via (TSV)-based 3D IC partitioning has focused on minimizing the number of TSVs to reduce costs. Partitioning methods based on heterogeneous integration have emerged as viable approaches for cost optimization. Leveraging mature processes to manufacture not timing-critical blocks can yield cost benefits. Nevertheless, none of the previous 3D partitioning work has focused on reducing the overall cost, including both design and manufacturing costs, for heterogeneous 3D integration. Moreover, throughput constraints have not been considered. This article presents a cost-aware integer linear programming-based formulation and a heuristic algorithm that partition the functional blocks in the design into different technological groups. Each group of functional blocks will be implemented using a particular process technology, and then integrated into a 3D IC. Our results show that 3D heterogeneous integration chip implementation can reduce overall cost while satisfying various timing constraints.

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors.

The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.

Morphology Control and Mechanism of Different Bath Systems in Cu/SiCw Composite Electroplating.

With the rapid development of electronic technology and large-scale integrated circuit devices, it is very important to develop thermal management materials with high thermal conductivity. Silicon carbide whisker-reinforced copper matrix (Cu/SiCw) composites are considered to be one of the best candidates for future electronic device radiators. However, at present, most of these materials are produced by high-temperature and high-pressure processes, which are expensive and prone to interfacial reactions. To explore the plating solution system suitable for SiCw and Cu composite electroplating, we tried two different Cu-based plating solutions, namely a Systek UVF 100 plating solution of the copper sulfate (CuSO4) system and a Through Silicon Via (TSV) plating solution of the copper methanesulfonate (Cu(CH3SO3)2) system. In this paper, Cu/SiCw composites were prepared by composite electrodeposition. The morphology of the coating under two different plating liquid systems was compared, and the mechanism of formation of the different morphologies was analyzed. The results show that when the concentration of SiCw in the bath is 1.2 g/L, the surface of the Cu/SiCw composite coating prepared by the CuSO4 bath has more whiskers with irregular distribution and the coating is very smooth, but there are pores at the junction of the whiskers and Cu. There are a large number of irregularly distributed whiskers on the surface of the Cu/SiCw composite coating prepared with the copper methanesulfonate (Cu(CH3SO3)2) system. The surface of the composite is flat, and Cu grows along the whisker structure. The whisker and Cu form a good combination, and there is no pore in the cross-section of the coating. The observation at the cross-section also reveals some characteristics of the toughening mechanism of SiCw, including crack deflection, bridging and whisker pull-out. The existence of these mechanisms indicates that SiCw plays a toughening role in the composites. A suitable plating solution system was selected for the preparation of high-performance Cu/SiCw thermal management materials with the composite electrodeposition process.

Spray mist-assisted drilling of through silicon vias (TSV) using nanosecond laser: Influence of CNT nanofluid

Through Silicon Vias (TSV) are crucial in semiconductor technology for vertically connecting multiple stacks in 3D packaging. High aspect ratio, smooth and slightly tapered TSVs enhance layout efficiency and void-free filling. Being contact-less and dry-etching process, laser machining is a promising technique to fabricate TSVs. A percussion laser drilling approach was used to fabricate TSVs on a 500 μm thick silicon wafer with a 1064 nm ns laser. Four environments such as air, compressed air jet, water mist, carbon nanotube (CNT) fluid mist were employed to assess laser machining effects on TSV performance in terms of entrance and exit diameters, recast layer, side wall damage, and taper angle. Optimized process parameters (laser pulse energy and pulse number) were derived from an ANN prediction model. Laser drilling under CNT mist produced relatively circular (entrance diameter), straight, and clean TSVs. Reduced debris redeposition was observed under air jet, water mist, and CNT mist compared to air. Minimal sidewall damage occurred under water mist and CNT mist as compared to those machined in air and air jet. CNT mist yielded TSVs with less recast layer (∼7 μm), taper angle (∼1.05 deg.), and heat affected zone (HAZ) thickness (∼50 μm). Enhanced machining quality may be attributed to increased thermal conductivity of CNT nanofluid and pressurized mist flow rate, improving cooling and debris removal. Furthermore, a detailed investigation of TSV using SEM was performed and the findings were compared to those of other research groups.

An ultra-deep TSV technique enabled by the dual catalysis-based electroless plating of combined barrier and seed layers

Silicon interposers embedded with ultra-deep through-silicon vias (TSVs) are in great demand for the heterogeneous integration and packaging of opto-electronic chiplets and microelectromechanical systems (MEMS) devices. Considering the cost-effective and reliable manufacturing of ultra-deep TSVs, the formation of continuous barrier and seed layers remains a crucial challenge to solve. Herein, we present a novel dual catalysis-based electroless plating (ELP) technique by tailoring polyimide (PI) liner surfaces to fabricate dense combined Ni barrier/seed layers in ultra-deep TSVs. In additional to the conventional acid catalysis procedure, a prior catalytic step in an alkaline environment is proposed to hydrolyze the PI surface into a polyamide acid (PAA) interfacial layer, resulting in additional catalysts and the formation of a dense Ni layer that can function as both a barrier layer and a seed layer, particularly at the bottom of the deep TSV. TSVs with depths larger than 500 μm and no voids are successfully fabricated in this study. The fabrication process involves low costs and temperatures. For a fabricated 530-μm-deep TSV with a diameter of 70 μm, the measured depletion capacitance and leakage current are approximately 1.3 pF and 1.7 pA at 20 V, respectively, indicating good electrical properties. The proposed fabrication strategy can provide a cost-effective and feasible solution to the challenge of manufacturing ultra-deep TSVs for modern 3D heterogeneous integration and packaging applications.

Wafer Scale Insulation of High Aspect Ratio Through-Silicon Vias by iCVD.

In microelectronics, one of the main 3D integration strategies consists of vertically stacking and electrically connecting various functional chips using through-silicon vias (TSVs). For the fabrication of the TSVs, one of the challenges is to conformally deposit a low dielectric constant insulator thin film at the surface of the silicon. To date, there is no universal technique that can address all types of TSV integration schemes, especially in the case requiring a low deposition temperature. In this work, an organosilicate polymer deposited by initiated chemical vapor deposition (iCVD) was developed and integrated as an insulating layer for TSVs. Process studies have shown that poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (P(V3D3)) can present good conformality on high aspect ratio features by increasing the substrate temperature up to 100 °C. The trade-off is a moderate deposition rate. The thermal stability of the polymer has been investigated, and we show that a thermal annealing at 400 °C (with or without ultraviolet exposure) allows the stabilization of the dielectric films by removing residual oligomers. Then, P(V3D3) was integrated in high aspect ratio TSV (10 × 100 μm) on 300 mm silicon wafers using a standard integration flow for TSV metallization. Functional devices were successfully fabricated (including daisy chains of 754 TSVs) and electrically characterized. Our work shows that the metallization barrier should be carefully selected to eliminate the appearance of voids at the top corner of the TSV after the Cu annealing step. Moreover, an appropriate integration process should be used to avoid the appearance of cohesive cracks in the liner. This work constitutes a first proof of concept of the use of an iCVD polymer in a quasi-industrial microelectronic environment. It also highlights the benefit of iCVD as a promising technique to deposit conformal dielectric thin films in a microelectronic pilot line environment.

Constructal design of comb-shaped high thermal conductivity channel in a stacked chip

A model of stacked chip with comb-shaped high thermal conductivity channel (HTCC) is established. With fixed number of through‑silicon vias (TSVs), constructal designs of comb-shaped HTCC are performed with single-degree-of-freedom (DOF), two-DOF and three-DOF optimizations, and effects of heat generation rate per volume (HGRPV) of device layer, HGRPV of TSV and filling materials of HTCC on its optimal construct and maximum temperature difference (MTD) in stacked chip are analyzed. Furtherly, constructal design of two-stage branched comb-shaped HTCC is studied. The optimal constructs of comb-shaped HTCC are obtained under single-DOF, two-DOF and three-DOF optimizations, which make the MTD of stacked chip reach the minimum. The minimum MTD obtained by three-DOF optimization is 43.74 K, which is 1.21 K and 0.45 K lower than that obtained by single-DOF and two-DOF optimizations, respectively. Compared with the initial design, the MTD under optimizations of single-, two- and three-DOFs decreased by 2.8%, 4.5% and 5.5%, respectively. Filling materials of HTCC have effect on optimal constructs of comb-shaped HTCC, however, the HGRPVs of device layer and TSV have not. The first-stage branches of two-stage branch comb-shaped HTCC are close together by constructal design, so embedding single-stage branch comb-shaped HTCC is more beneficial to heat dissipation of stacked chip.