Through Glass Via Research Articles

Physics based scalable inductance model for three-dimensional solenoid inductors

A physics based close form inductance model for three-dimensional (3-D) solenoid inductors with ground shileding is proposed in this letter. The expressions are derived in full consideration of partial self inductance and mutual inductance. The proposed model is extracted based on the process parameters and design parameters without any optimization. The 3-D inductor samples are fabricated on glass substrate by Through Glass Via (TGV) process. The accuracy of the proposed model is validated by comparing the results from the 3-D full-wave electromagnetic solver High Frequency Simulator Structure (HFSS) and measurement.

The interfacial reliability of through-glass vias for 2.5D integrated circuits

PurposeGlass is a promising interposer substrate for 2.5 D integration; yet detailed analysis of the interfacial reliability of through-glass vias (TGVs) has been lacking. The purpose of this paper is to investigate the design and material factors responsible for the interfacial delamination in TGVs and identify methods to improve reliability.Design/methodology/approachThe interfacial reliability of TGVs is studied both analytically and numerically. An analytical solution is presented to show the dependence of the energy release rate (ERR) for interfacial delamination on the via design and the thermal mismatch strain. Then, finite element analysis (FEA) is used to investigate the influence of detailed design and material factors, including the pitch distance, via aspect ratio, via geometry and the glass and via materials, on the susceptibility to interfacial delamination.FindingsERR for interfacial delamination is directly proportional to the via diameter and the thermal mismatch strain. Thinner wafers with smaller aspect ratios show larger ERRs. Changing the via geometry from a fully filled via to an annular via leads to lower ERR. FEA results also show that certain material combinations have lower thermal mismatch strains, thus less prone to delamination.Practical implicationsThe results and approach presented in this paper can guide the design and development of more reliable 2.5 D glass interposers.Originality/valueThis paper represents the first attempt to comprehensively evaluate the impact of design and material selection on the interfacial reliability of TGVs.

Steering of surface discharges on through-glass-vias combined with high-density nonequilibrium atmospheric pressure plasma generation

The concept of using a glass substrate with fine through-holes filled with metal, called through-glass-vias (TGVs), for an inner wall of an enclosure of a nonequilibrium atmospheric pressure plasma source was validated to extend its processing area with high plasma densities maintained. When applying the TGV substrate into an inner wall of the plasma source, the generated discharge was less likely to drift along with the gas flow, which resembled the behavior of locally high electric fields of the plasma source, called the creeping mode. The decrease in breakdown voltage was also observed. These phenomena are caused by the TGV areas acting as a steering control material in the enclosure of the plasma source. The location of the TGV areas affected the behavior of the generated plasma. The shape of the plasma was accomplished to arbitrarily and locally control by the placement of TGVs.

Development of a μ-PIC with glass substrate aiming at high gas gain

Micro pixel chambers (μ-PICs), which are a type of the micro-pattern gas chambers, are usually manufactured using the printed-circuit-board (PCB) technology. However, recent application projects have begun to require higher gas gains and finer position resolution than those obtainable with current μ-PICs. It is difficult to improve the electrode structure to achieve these improvements because PCB technology limits the precision of electrode fabrication and the thickness of the substrate. We have therefore adopted micro-electro-mechanical-systems (MEMS) technology and developed the first prototype of a through-glass-via (TGV) μ-PIC. This prototype TGV μ-PIC worked well, achieving a maximum gain of approximately 20,000 and an energy resolution of 20.6% (FWHM) at 5.9 keV over the whole 5 × 5 cm2 detection area.

Micro-Compression of Freestanding Electroplated Copper Through-Glass Vias

In this study, the micro-compression of freestanding copper (Cu) through-glass vias (TGVs) is presented. An innovative approach was developed to obtain freestanding Cu TGVs where the Cu overburden was used as a bottom platen for the micro-compression test, allowing the mechanical responses of individual TGVs to be directly obtained. From the measured mechanical responses, the average yield strength of the Cu TGVs was determined as 123 MPa with a standard deviation of 7.85MPa. The yield strength values of the six tested TGVs were in good agreement, indicating a reliable and repeatable test procedure. This value was found to be slightly lower than the yield stress values of Cu TSVs, but within the range reported for electroplated Cu. Factors that affect the mechanical properties of the Cu TGVs, including electroplating parameters and microstructure variation, were discussed. The sample preparation and the micro-compression test methods demonstrated in this study can be readily adopted for TGVs subjected to various fabrication and annealing conditions, which will enable the fine-tuning of the processing parameters to produce Cu TGVs with desirable properties for a specific application. Results from this test will also provide valuable input for predictive thermo-mechanical models to enable the development of reliable glass interposers.

Numerical and experimental analysis of high-aspect-ratio micro-tool electrode fabrication using controlled electrochemical machining

Numerical and experimental analysis of high-aspect-ratio micro-tool electrodes fabrication using a controlled electrochemical machining (ECM) technique is reported. The evolution of the tool electrode shape was first predicted using a finite element method-based numerical simulation and then validated with the detailed experiments. The effects of machining voltages and the machining durations on the change in the tool electrode profile were investigated. High-carbon steel was chosen as an electrode material due to its lower cost, good electrical conductivity, and easy availability. A 5% (i.e., 5 gm of NaCl in 100 ml of deionized water) NaCl solution was used as the electrolyte. The tool profiles predicted using the FEM-based numerical model showed an excellent matching trend with the ECM experimental results. The role of the black surface film formed on the electrode surface was found to be significant. The tool electrodes having an average diameter of 60 µm and an aspect ratio of more than 75 were fabricated at the optimized machining parameters. These single-tip micro-tool electrodes were used to create through-hole in a 400-µm-thick glass substrate by electrochemical discharge machining. The obtained ECM process parameters were used to create multiple electrodes having a tip size of 130 µm and having a smooth surface. These through-holes were filled with copper to form 3D interconnects, i.e., through-glass vias, which are required in the radio-frequency MEMS applications and 3D packaging.

Characterization and Electrical Performance of Glass Diplexer Modules

Abstract A process has been developed to manufacture a glass diplexer module using conventional laminate circuit board processes that have been adapted to handle glass substrates. Over the past few years we have evaluated both Cu plating and electrically conductive adhesives (ECAs) to produce a through glass via (TGV). From this work, it has been determined that Cu plating is a preferred process to form a robust TGV in a manufacturing environment. A Cu plated TGV nicely compliments our semi-additive plating (SAP) processes to produce fine line Cu circuitry on both sides of a glass substrate. In addition, we have successfully laminated an Ajinomoto Buildup Film (ABF) to both sides of a glass substrate having TGVs. The ABF completely filled the vias and also maintained uniform flatness on both sides. The resulting interposer was very flat and suitable for the next level of Cu plating using SAP. The ABF material was able to form high quality blind vias using laser drilling. A more comprehensive characterization of the glass diplexer modules will be presented, which will include X-sections of a double-sided Cu circuitry and Cu MIM (metal-insulator-metal) capacitors and inductors. In addition, the first set of electrical test data will be presented and compared with the modeling work done to date.

Thin Glass Substrates with Through-Glass Vias.

Abstract Glass substrates with fine-pitch through-glass via (TGV) technology is a promising approach to system in a package (SIP) integration. Millimeter wave applications, in particular, benefit from the superior RF properties, dimensional stability, and surface properties of glass. Glass can be made in very thin sheets (<200 um) which aids in integration and eliminates the need for back-grinding operations. The biggest challenge to adopting glass as a microelectronics packaging substrate is the existence of gaps in the supply chain, caused primarily by the difficulty in handling large, thin glass substrates using existing automation and processing equipment. This paper presents a temporary bonding technology that allows the substrates to be processed in a semiconductor fab environment without the need to modify existing equipment.

Effect of tool electrode roughness on the geometric characteristics of through-holes formed by ECDM

Experimental investigation into the effect of tool electrode roughness on the geometric characteristics of through-holes formed in glass substrate by electrochemical discharge machining (ECDM) is reported. Single tip tool electrodes having different surface roughnesses were fabricated by the wire-electric discharge machining (wire-EDM). These tools were then used to produce through-holes in a 400 μm thick glass substrate by ECDM. The surface roughness of the used tools was further improved by a cost-effective electrochemical finishing (ECF) process to re-use the tools for through-hole machining. ECF also helped in removing the debris deposited on the tool during the ECDM. Through-hole geometric characteristics were analyzed by measuring the overcut and heat-affected zone (HAZ) width for through-holes fabricated by tools having different surface roughness. Experimental results showed that the discharges generated were inconsistent and aggressive for tool electrodes having higher surface roughness, which resulted in higher overcut and higher surface damages. The radial overcut, and the HAZ width were reduced significantly when the ECF finished tool electrodes having a lower surface roughness were used. Improvement in the geometric characteristics of through-holes was observed due to thin hydrogen gas film formation around the tool electrodes during the ECDM. Current-time behavior showed that the mean discharge current was reduced when tool electrodes having reduced surface roughness were used. The bottom-up electrodeposition technique was then utilized to fill the through-holes with electroplated copper. Through-holes fabricated by optimized process parameters were filled with copper, thus fabricating through-glass vias (TGVs) which has promising applications in radio-frequency MEMS and electronic packaging.

Nanocrystalline diamond-glass platform for the development of three-dimensional micro- and nanodevices

Low-cost and robust platforms are key for the development of next-generation 3D micro- and nanodevices. To fabricate such platforms, nanocrystalline diamond (NCD) is a highly appealing material due to its biocompatibility, robustness, and mechanical, electrical, electrochemical, and optical properties, while glass substrates with through vias are ideal interposers for 3D integration due to the excellent properties of glass. However, developing devices that comprise NCD films and through glass vias (TGVs) has rarely been attempted due to a lack of effective process strategies. In this work, a low-cost process — free of photolithography and transfer-printing — for fabricating arrays of TGVs that are sealed with suspended portions of an ultra-thin NCD film on one side is presented. These highly transparent structures may serve as a platform for the development of microwells for single-cell culture and analysis, 3D integrated devices such as microelectrodes, and quantum technologies. The process is demonstrated by fabricating TGVs that are sealed with an NCD film of thickness 175 nm and diameter 60 μm. The technology described can be extended by replacing NCD with silicon nitride or silicon carbide, allowing for the development of complex heterogeneous structures on the small scale.

Design and Demonstration of Glass Panel Embedding for 3D System Packages for Heterogeneous Integration Applications

Abstract This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integration. High-density logic-memory integration, today, is built predominantly using interposers which are fundamentally limited in assembly pitch and interconnect lengths, and they also are expensive as the package sizes increase. On the other hand, high-frequency applications continue to use laminates which are also limited by package size and ability to integrate many components. Wafer-level fan-out (WLFO) packaging promises better performance and form factor at lower costs, but current WLFO packages are mold-based and hence are limited to small packages. This article presents a 3D packaging technology using glass panel embedding (GPE) for high-performance with potential for large body size heterogeneous integration applications. The tailorable coefficient of thermal expansion of glass allows a reliable direct board attach of large GPE packages that not only benefits the form factor and signal speed but also provides radical benefits to power delivery. Unlike interposers and silicon bridges, GPE packages are not bump-limited and can support I/O densities comparable with backend-of-line with silicon-like redistribution wiring at much lower costs. The fundamental limitations such as die shift and poor dimensional stability of current organic WLFO packages are addressed by parametric process improvements to reduce die shift to <2 μm while also improving the RDL surface planarity for high-yielding fine-line structures and integrating through glass via (TGV) in the fan-out region for 3D packaging. This article describes the fabrication process for 3D GPE, leading to demonstration of a technology using embedding of chips with all-Cu interconnections at 40-μm I/O pitch with TGVs at 300-μm pitch, thus enabling double-side RDL and assembly of chips to achieve three levels of device integration.

Design, fabrication, and radio frequency property evaluation of a through-glass-via interposer for 2.5D radio frequency integration

In this paper, a through-glass-via (TGV) interposer for 2.5D radio frequency (RF) integration is presented. A coplanar waveguide (CPW) transmission line with grounded TGVs on one side interconnects with the mounted RF devices, and an electrical ground plane on the other side. Tapered TGVs are fabricated using a combined method of sandblasting and thinning/polishing process to achieve precise control of the profile of the vias and improve uniformity. The TGVs are metalized by conformal copper (Cu) electroplating to form a vertical interconnection between the upper and lower metal layers, which can maintain RF performance and avoid thermal stress issues. The CPW transmission lines with electrically grounded TGVs and test structures are designed, fabricated and tested to evaluate the TGV’s RF performance and suitability for 2.5D RF integration. The RF measurements show that the insertion loss is about 0.13 dB mm−1@10 GHz for the CPW line with grounded TGV which is less than 0.1 dB@10 GHz for a single TGV. We analyzed S parameter for the tests and simulations when taking into account various factors in the manufacturing process, such as the surface roughness and metal resistivity. The results provide a research direction for the optimization of the parameters in the follow-up study. In addition, a 2.5D RF receiver module based on the proposed TGV interposer in the L-band is assembled and validated. The gain value of the TGV interposer integrated RF module is about 14.4 dB, which is close to the theoretical value.

Laser-drilling formation of through-glass-via (TGV) on polymer-laminated glass

A three-dimensional (3D) glass integrated passive device (IPD) is an evolutionally advanced configuration to dramatically reduce the electronics form factor and manufacturing cost of current IPDs by introducing ultra-thin glass with through-glass-vias (TGVs). A defect-free TGV formation technology in polymer-laminated glass substrates is required to realize a highly reliable 3D glass IPD. This paper discusses mechanisms of each defect formation in the use of several types of lasers to explore suitable technology for defect-free drilling in polymer-laminated glass.

Microprobe electrode array with individual interconnects through substrate using silicon through-glass via

This paper presents the fabrication and measurements of a vertical out-of-plane microprobe electrode array with individual interconnects through the substrate using a silicon through-glass via (TGV) with transparent properties. The TGV was fabricated using a low-resistance silicon (LRS) via and the glass reflow process. The microprobe structure was formed by multiple deep reactive ion etching and reactive ion etching processes using one-step photolithography and a single etch mask. The height and pitch of the microprobe are designed to be 90 μm and 210 μm, respectively. Cr and Au conductive layers were deposited and patterned on the silicon microprobe structure. A parylene-C thin film was used as an insulating layer and it was etched only at the tip-end through the self-alignment fabrication process using a thick photoresist to expose the conductive part. Each microprobe electrode was independently connected to the backside of the substrate through the silicon TGV. The single via resistance was measured to be 1.26 ± 0.041 Ω. To verify the electrochemical characteristics of the microprobe electrodes with individual interconnects, the steady-state limiting current through the redox reaction was measured by the cyclic voltammetry method for each electrode. The measured steady-state peak current of the microprobe electrode was compared with the theoretical calculation. Further, the electrode impedance was measured and the equivalent circuit analysis was constructed using the Zview impedance modeling software. Experiments were conducted to measure the impedance of 16 microprobe electrodes, and it was confirmed that the impedance did not exceed 1 MΩ at 1 kHz. Then, primary rat cortical neuron cells (DIV 7) were cultured on the fabricated microprobe electrodes and neural spike signals were successfully measured. Also, the light transmittance experiment was conducted to measure the transparency of the TGV structure fabricated through the glass reflow process.

Through Glass Vias for hermetically sealed High Frequency Application

In this work we demonstrate the fabrication and use of a glass interposer platform with Through Glass Vias (TGVs) for high frequency applications. The platform is part of a versatile hermetically sealed glass package including passive and active devices (radar sensor, pressure sensors, infrared sensors). Glass has ideal properties for such applications, like excellent chemical resistance, mechanical strength and low costs. The hermetic sealing allows the seamless operation in hazardous environments. The TGVs may be deployed, for instance, in miniaturized sensor systems as vertical DC and RF interconnections with reduced parasitics for improved performance of the sealed device, while maintaining the hermetic sealing. TGVs provide a superior RF performance compared to bonding wires for frequencies >20 GHz and will provide larger bandwidths. TGVs improve the performance drastically and will give us an easy way to provide a hermitically sealed connection to the inner circuitries of the package. We investigate the whole process chain of the fabrication of the metallized TGVs. Initially 200 mm glass wafer with a thickness of 500 μm are used. Vias are created by laser-induced deep etching (LIDE). Subsequently, selective metallization of wafer surface areas and TGV sidewalls is carried out. Vias with diameters ranging from 50 μm to 1mm are created. The wafer thickness is reduced to 465 μm during the via production. Thus vias with an aspect ratio of 1:9 to 2:1 are created on one wafer. The vias with the high-aspect ratio are filled by sputtering with an appropriate seed layer for electroplating. Depending on the via geometry and the aspect ratio, normal DC sputtering is not viable. Thus, High Power Impulse Magnetron Sputtering (HIPIMS) is utilized to deposit a thin film of titanium and copper. Titanium served as the adhesion layer and copper is used as the conductive seed layer for the following electroplating step. Then, electroplating is carried out to line the different sized TGVs and create a conducting path through the wafer. Afterwards, the metallization in the vias has to be exposed by removing only the plated copper and sputtered titanium on top of the wafer by a combination of etching and chemical mechanical polishing. In the following steps, the front and backside are sputtered and coated with a resist to allow electroplating of the RDL on both backside and front side. Finally, the wafer is diced and measured. The LIDE process shows excellent repeatability with respect to the position and shape of the TGVs on all axes. The repeatability of the shape is critical for the following TGV metallization and the matching of the simulated RF behaviour compared to the behaviour of the fabricated structures. The metallization process of the TGVs shows very promising results regarding the repeatability of the formation of the TGVs and the metallization inside the vias. Different shapes and dimensions of vias could be metallized with the same process, which makes it stable against deviations in the structures to be fabricated on the wafer The measured RF properties of the realized structures are very promising and showing that the usage of glass and TGVs improves the performance in the millimetre wave regime significantly, compared to conventional bonding wires.

Processing Through Glass Via (TGV) Interposers

For the next generation of 3D-IC applications, glass offers many desirable properties that make it an ideal interposer. In order to realize these applications, it becomes necessary to be able to deposit a Cu layer on both surfaces as well as in the glass via. In this paper we will present results of interposers that have fine line circuitry on both sides of the glass and have through glass vias (TGVs). One major challenge is how to create a TGV using either electrically conductive adhesives (ECAs) or Cu plating methods to achieve a high conductivity and reliable via connection. Most work to date uses ECA materials to fill the TGV, however, many of these ECA materials have limitations in that they cannot withstand temperatures in excess of 400°C, are not hermetic and do not have the electrical properties of bulk Cu. In the first phase of our work, we have evaluated different commercially available ECA materials to fill the glass vias. A major challenge in using these materials is how to effectively fill the vias. Our test vehicle has a TGV with dimensions of 50um diameter and a 300um thickness on 2″ × 2″ glass substrate. A positive pressure screen printing process was used to fill the vias. These ECA materials exhibited a very high viscosity, due to the high Cu metal filler content, which made them very difficult to fill. Different pressures, squeegee speeds, and standoff conditions were evaluated to arrive at an optimized process to effectively fill the glass vias. A tilted X-ray inspection approach was used to characterize the yield for ECA hole fill. A DOE of different sintering conditions was conducted to determine how to maximize the electrically conductivity of the paste. From this work we will show the impact of sintering conditions on electrical conductivity and hermeticity. In parallel, we have developed a process to Cu plate a TGV. In this approach, a dry deposition process was used to produce a conductive seed layer in the via having a diameter of 100um and a total substrate thickness of 300um. We proceeded to use a Cu electroplating process to plate up a conformal Cu layer in the glass via. In this work we have pattern plated circuitry on both surfaces along with the via to produce a glass interposer. In addition, we were able to deposit a very thin layer of Si3N4 between two thick Cu metal layers on the topside of a glass interposer to produce a capacitor. The success of plating a TGV also enables the formation of inductors in a glass substrate. An organic dielectric layer using an Ajinomoto Buildup Film (ABF) was used to create a single buildup layer on the glass interposer. The combination of these individual technologies allows the capability to manufacture a glass interposer for advanced packaging applications. A discussion of the challenges associated in building glass interposers will be presented, which will include examples of recent builds of a double-sided Cu circuitry glass interposer and a diplexer module having Cu MIM (metal-insulator-metal) capacitors and inductors for RF applications.

Fabrication and Characterization of Through-Glass Vias by the ECDM Process

Fabrication and characterization of electrodeposited copper filled through-glass vias (TGV) are demonstrated on full-scale fused silica wafer for the first time by a simple combination of electrochemical discharge machining and bottom-up copper electrodeposition. Due to lower cost and easy availability, stainless steel was chosen as tool electrode. Wire-EDM was used to create customized multi-tip tool electrodes that were used to create through-holes in a 520 μm thick fused silica substrate in less than 10 min. The average tool wear ratio was measured to be around 16. Due to the non-conductive nature of fused silica, these through-holes did not require any insulation and barrier layer and were filled with electrodeposited copper. I-V measurements of the TGVs showed a linear ohmic behavior. The Kelvin resistances of the fabricated TGVs were measured to be ranging from 242 mΩ to 275 mΩ. The average resistance of the fabricated Cu filled TGVs was 256 mΩ. The variation in the TGV resistance was less than ±8%. Due to its simplicity, this technique can be used in the fabrication of the integrated radio-frequency (RF) passive devices such as inductors and 3D packaging applications.

Photosensitive Glass-Ceramics for Heterogeneous Integration

The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, II...

Research on Wafer-Level MEMS Packaging with Through-Glass Vias.

A MEMS fabrication process with through-glass vias (TGVs) by laser drilling was presented, and reliability concerns about MEMS packaging with TGV, likes debris and via metallization, were overcome. The via drilling process on Pyrex 7740 glasses was studied using a picosecond laser with a wavelength of 532 nm. TGVs were tapered, the minimum inlet diameter of via holes on 300 μm glasses was 90 μm, and the relative outlet diameter is 48 μm. It took about 9 h and 58 min for drilling 4874 via holes on a four-inch wafer. Debris in ablation was collected only on the laser inlet side, and the outlet side was clean enough for bonding. The glass with TGVs was anodically bonded to silicon structures of MEMS sensors for packaging, electron beam evaporated metal was used to cover the bottom, the side, and the surface of via holes for vertical electrical interconnections. The metal was directly contacted to silicon with low contact resistance. A MEMS gyroscope was made in this way, and the getter was used for vacuum maintenance. The vacuum degree maintained under 1 Pa for more than two years. The proposed MEMS fabrication flow with a simple process and low cost is very suitable for mass production in industry.

Design of a 3D Wilkinson power divider using through glass via technology * * Projected supported by the National Natural Science Foundation of China (Nos. 61771268, 61571248, U1709218), the Science and Technology Fund of Zhejiang Province (No. 2015C31090), the Natural Science Foundation of Zhejiang (No. LY17F040002), and the K. C. Wong Magna Fund in Ningbo University.

Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study, through glass vias (TGVs) are used to implement 3-D inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-D Wilkinson power divider is designed and analyzed. Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.