Through Silicon Via Structure Research Articles

Fabrication and RF Property Evaluation of High-Resistivity Si Interposer for 2.5-D/3-D Heterogeneous Integration of RF Devices

In this paper, a high-resistivity silicon (HR-Si) interposer integrated with through-silicon via (TSV) electrically grounded coplanar waveguide (CPW) line is presented for 2.5-D/3-D heterogeneous integration of radio frequency (RF) microelectronics devices. In addition, design of TSV interconnection composed of two coaxial ladder-hollow-annular Cu (copper) TSVs of different diameters is utilized to maintain a sufficient freedom for strict standard cleaning to avoid Si resistivity degradation. The formation of the coaxial ladder TSV structure is more beneficial to the subsequent plating process because it reduces the aspect ratio of TSV vias. Hollow-annular Cu TSV is manufactured in order to reduce the problem of mismatch in coefficient of thermal expansion among TSV’s constituent materials. A layer of Au (aurum) film is utilized to passivate the exposed Cu surface of Si interposer. Au is widely used in III–V groups’ devices because of the good compatibility with photonic integrated circuits, conductivity, and corrosion resistance. HR-Si interposer with TSV grounded CPW line and test structure is fabricated and characterized. With the monitoring test results, it can be found that it changes little in the resistivity of Si substrate, though the whole process, which is a basic requirement for RF performance. RF property test results show that the insertion loss is about −0.20 dB/mm at 10 GHz for the presented TSV grounded CPW line and −0.02 dB per TSV. These test results are better than the traditional design. To verify its applicability to 2.5-D/3-D heterogeneous integration, RF microelectronics die is assembled on TSV interposer and tested, and the test results prove that it works properly.

Insights into Laser Ablation Processes of Heterogeneous Samples: Toward Analysis of Through-Silicon-Vias.

State-of-the-art three-dimensional very large-scale integration (3D-VLSI) relies, among other factors, on the purity of high-aspect-ratio Cu interconnects such as through-silicon-vias (TSVs). Accurate spatial chemical analysis of electroplated TSV structures has been proven to be challenging due to their large aspect ratios and their multimaterial composition (Cu and Si) with distinct physical properties. Here, we demonstrate that these structures can be accurately analyzed by femtosecond (fs) laser beam ablation techniques in combination with ionization mass spectrometry (LIMS). We specifically report on novel preparation approaches for the postablation analysis of craters formed upon TSV depth profiling. The novel TSV sample preparation is based on deep and material-selective reactive-ion etching of the Si matrix surrounding the Cu interconnects thus facilitating systematic focused-ion-beam (FIB) investigations of the high-aspect-ratio TSV structures upon ablation. The particular structure of the TSV analyte combined with the ⌀beam > ⌀Cu-TSV condition allowed for an in-depth investigation of fundamental laser ablation processes, particularly focusing on the redeposition of ablated material at the inner side-walls of the LIMS craters. This phenomenon is of imminent importance for the ultimate quantification in any laser ablation-based depth profiling. In addition, we have developed a new method which allows the unambiguous determination of the crossing-point of the Si/Cu||bare Si interface upon Cu-TSV depth profiling which is based on pronounced, depth-dependent changes in the mass-spectrometric detection of those Si xy+ species formed upon the LIMS depth erosion.

Anomalous ${C}$ – ${V}$ Inversion in TSVs: The Problem and Its Cure

The metal–insulator–semiconductor capacitor formed by a through-silicon via (TSV) with its insulating layer and the p-type Si substrate may show an anomalous inversion behavior in the ${C}$ – ${V}$ characteristic. The dominant cause is the presence of positive charges in the backside (BS) passivation layer. In this paper, a dedicated test structure is proposed and characterized to confirm this hypothesis. Furthermore, a charge-free oxide/nitride BS passivation layer for preventing the anomalous ${C}$ – ${V}$ inversion, proposed in our previous work, is validated by experimental results on TSV structures manufactured up to the complete BS metallization processing.

Crosstalk noise minimization in novel through silicon via structures

In recent trends, through silicon via (TSV) is essential Technologies for 3-D IC integration because of its short interconnects length and high interconnect density. Beyond the existing structure of TSV, this paper provides a novel structure to investigate the crosstalk effect and same is simulated by using a SPICE simulator and 3-D field solver. The structure of the TSV comprises of copper surrounding by insulating liner, and silicon substrate. In existing structures, silicon dioxide (Sio2) is used as insulating liner because of its material compatibility with silicon substrate. Several researches provide the problem of using Sio2 is due to its high dielectric constant; as a consequence delay will increase. Therefore, Sio2 is not appropriate for high performance applications. In this work, a novel TSV structure is reported to improve the TSV performance which uses poly-propylene polymer liner instead of oxide liner. Signal TSV is enclosed by using a poly-propylene liner and amid the analysis with doping region is created around the ground TSV. For comparison purposes, conventional and proposed TSV structures are simulated. The proposed TSV’s structure simulation results in 30% decrease in crosstalk over existing TSV structures.

Effects of SiO2 film thickness and operating temperature on thermally-induced failures in through-silicon-via structures

In the present study, the experimental results of the thermally induced failure (fracture) time for the components of copper through‑silicon via (TSV) structures and the time for electrical current breakdown (TBD) are obtained to investigate the effects of the thickness of the SiO2 film and the operating temperature. The numerical scheme is also developed to solve the distributions of transient temperature and stress in the specimen and the equivalent stress/strain for the elements in the Ti, SiO2 and Si components of the TSV structure. The equivalent element stress solutions incorporating with the Johnson-Cook (J-C) fracture model are provided to identify the earliest failure element and time in each of these three components and the TBD of the structure via the definition for the D factor. The applied models and numerical scheme are confirmed to be trustworthy from the comparison of the numerically predicted and experimental results for these failure time parameters. The effects of the operating temperature of specimen's bottom surface and the film thickness of SiO2 on these time parameters have been evaluated precisely. The TBD time is elongated by increasing the thickness of either SiO2 or Ti film if the bottom surface is operating at a fixed temperature. The earliest failure time (tfailure) for the components of Ti, SiO2 and Si wafer and the TBD are always reduced by the rise of operating temperature.

Defect localization of metal interconnection lines in 3-dimensional through-silicon-via structures by differential scanning photocapacitance microscopy

We report a differential scanning photocapacitance microscopy technique based on the detection of light-induced capacitance changes allowing mapping of metal interconnection line defects in through-silicon-via (TSV) structures used in three-dimensional (3-D) integration technology. Due to the photosensitive silicon depletion capacitance, observation of the photocapacitance response enables non-destructive two-dimensional (2-D) visualization of metallization line ruptures in TSV structures. We demonstrate the application of the proposed method on a TSV chain structure and reveal the location of the open metallization rupture.

Effect of Thermal Mechanical Behaviors of Cu on Stress Distribution in Cu-Filled Through-Silicon Vias Under Heat Treatment

Through-silicon vias (TSV) are facing unexpected thermo-mechanical reliability problems due to the coefficient of thermal expansion (CTE) mismatch between various materials in TSVs. During applications, thermal stresses induced by CTE mismatch will have a negative impact on other devices connecting with TSVs, even leading to failure. Therefore, it is essential to investigate the stress distribution evolution in the TSV structure under thermal loads. In this report, TSVs were heated to 450°C at different heating rates, then cooled down to room temperature after a 30-min dwelling. After heating treatment, TSV samples exhibited different Cu deformation behaviors, including Cu intrusion and protrusion. Based on the different Cu deformation behaviors, stress in Si around Cu vias of these samples was measured and analyzed. Results analyzed by Raman spectrums showed that the stress distribution changes were associated with Cu deformation behaviors. In the area near the Cu via, Cu protrusion behavior might aggravate the stress in Si obtained from the Raman measurement, while Cu intrusion might alleviate the stress. The possible reason was that in this area, the compressive stress $$ \sigma_{\theta }$$ induced by thermal loads might be the dominant stress. In the area far from the Cu via, thermal loads tended to result in a tensile stress state in Si.

Development of Stacking Process for 3D TSV (Through Silicon Via) Structure using Laser

Abstract TSV chips were designed and fabricated to investigate the effects of the types of the stacking process on the manufacturability. Two processes were compared: thermocompression and laser bonding. The pitch of UBMs, solder bumps, and TSVs were 50μm. A fluxing underfill was developed and used as a pre-applied underfill during the stacking process. The bonding profiles and the solder joint morphology based on the thermocompression and the laser bonding were compared.

High-Level Energy Estimation for Submicrometric TSV Arrays

The 3-D integration using through silicon vias (TSVs) is one of the most promising approaches to overcome the interconnect delay problem of current CMOS technologies. Nevertheless, the TSV energy consumption is not negligible due to the high capacitive coupling. This paper presents an abstract and yet accurate model to estimate the pattern-dependent energy consumption in arrays of TSVs; it is the first high-level model including the effects of the voltage-dependent metal–oxide–semiconductor (MOS) capacitances surrounding each TSV and a possible temporal misalignment between the input signals. We propose a regression method to estimate the dynamic size of the coupling capacitances as a function of the bit probabilities. Experimental results for real and synthetic data streams, a submicrometer 9-bit TSV array and a 65-nm technology show that the presented TSV energy model exhibits a maximum error of 5.53%, while the traditional high-level model shows errors of up to 79.77%. Furthermore, the new insights provided by our model reveal a possibility to easily boost the efficiency of existing low-power codes for TSV structures by over 10% without affecting the coding efficiency for the planar metal wires or the encoder complexity.

Analysis on annealing-induced stress of blind-via TSV using FEM

Copper-filled through silicon via (TSV) is a promising material owing to its application in high-density three-dimensional (3D) packaging. However, in TSV manufacturing, thermo-mechanical stress is induced during the annealing process, often causing reliability issues. In this paper, the finite element method is employed to investigate the impacts of via shape and SiO2 liner uniformity on the thermo-mechanical properties of copper- filled blind-via TSV after annealing. Top interface stress analysis on the TSV structure shows that the curvature of via openings releases stress concentration that leads to ~60 MPa decrease of normal stresses, σxx and σyy, in copper and ~70 MPa decrease of σxx in silicon. Meanwhile, the vertical interface analysis shows that annealing-induced stress at the SiO2/Si interface depends heavily on SiO2 uniformity. By increasing the thickness of SiO2 linear, the stress at the vertical interface can be significantly reduced. Thus, process optimization to reduce the annealing-induced stress becomes feasible. The results of this study help us gain a better understanding of the thermo-mechanical behavior of the annealed TSV in 3D packaging.

Characterizing Interfacial Sliding of Through-Silicon-Via by Nano-Indentation

In this paper, an experimental method is proposed to determine the shear sliding behavior of the interface between a copper through-silicon-via (TSV) and silicon. This interface was loaded in a nano-indentation experiment on specimens that were fabricated using focused-ion-beam milling. The elastic and plastic properties of the copper via were first characterized by micro-pillar compression experiments. The interfacial sliding is described by a cohesive zone model with a traction-separation relation including a linearly elastic part followed by frictional sliding at a constant shear traction. Both analytical and numerical models were developed for extracting the parameters of the traction-separation relation for the shear behavior of the interface. The average critical shear traction required to initiate interfacial sliding was found to be 77.2 MPa and the corresponding relative displacement across the interface was 182.7 nm, while the frictional shear strength was 25 MPa. The traction-separation relation with the extracted parameters may be used to study via extrusion and associated reliability analysis for integrated TSV structures.

A Study on the Thermomechanical Reliability Risks of Through-Silicon-Vias in Sensor Applications.

Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.

Fabrication of through-silicon via arrays by photo-assisted electrochemical etching and supercritical electroplating

This paper aims to fabricate high aspect ratio through silicon via (TSV) by photo-assisted electrochemical etching (PAECE) and supercritical CO2 copper electroplating. A blind-holed silicon array was first fabricated by PAECE. By studying the etching parameters, including hydrofluoric acid concentration, etchant temperature, stirring speed, tetrabutylammonium perchlorate (TBAP) content, and Ohmic contact thickness, an array of pores with a 1∶45 aspect ratio (height=250 μm and diameter=5.5 μm) was obtained successfully. Moreover, TBAP and Kodak Photo-Flo (PF) solution were added into the etchant to acquire smooth sidewalls for the first time. TBAP was added for the first time to serve as an antistatic agent in deionized water-based etchant to prevent side-branch etching, and PF was used to degasify hydrogen bubbles in the etchant. The effect of gold thickness over Ohmic contact was investigated. Randomized etching was observed with an Au thickness of 200 Å, but it can be improved by increasing the etching voltage. The silicon mold of through-holes was filled with metal using supercritical CO2 copper electroplating, which features high diffusivity, permeability, and density. The TSV structure (aspect ratio=1∶35) was obtained at a supercritical pressure of 2000 psi, temperature of 50°C, and current density of 30 mA/cm2 in 2.5 h.

Development and reliability study of 3D WLCSP for CMOS image sensor using vertical TSVs with 3:1 aspect ratio

3D wafer-level chip scale packaging (3D WLCSP) using via last through silicon via (TSV) technology is an ideal technology to meet small-form-factor, high I/O density, high-speed, short time to market and lower cost product requirements. In this study, process development and reliability evaluation of 3D WLCSP for CMOS Image Sensor (CIS) using vertical TSVs with 3:1 aspect ratio were presented. Key processes including wafer bonding, wafer backside grinding, silicon etch, bottom oxide etch, via cleaning, barrier/seed layer deposition, electroplating, redistribution layer (RDL) and ball grid array (BGA) formation were developed. Reliability of the developed WLCSP was characterized by various tests. The failed devices after reliability tests were analyzed using microstructure observation and finite element simulation for stress distribution of TSV structure. The results indicate that WLCSP with vertical via last scheme can provide a reliable, low-cost solution for the next-generation CIS requiring high density routing.

Processing Effect on Via Extrusion for TSVs in Three-Dimensional Interconnects: A Comparative Study

A comparative study has been performed to investigate the processing effects on via extrusion for through-silicon vias (TSVs) in 3-D integration. This paper is focused on three TSV structures with identical geometry but different processing conditions. The thermomechanical behavior, microstructure, via extrusion, and additives incorporated during electroplating are examined by various techniques, including the electron backscatter diffraction and the time-of-flight secondary ion mass spectroscopy. By comparing the stress, material, and via extrusion behaviors of the TSV structures, the effect of processing conditions, particularly electroplating and postplating annealing, on via extrusion are discussed.

Electrical Characterization of Coaxial Silicon–Insulator–Silicon Through-Silicon Vias: Theoretical Analysis and Experiments

Coaxial through-silicon via (TSV) provides an effective solution to achieve impedance matching, reduce transmission loss, and suppress interference or noise coupling in 3-D/2.5-D heterointegrated systems. This paper presents a fabrication friendly coaxial TSV configuration based on heavily doped silicon–insulator–silicon (SIS) structure, whose electrical characteristics are studied through deriving analytical solution, performing numerical simulation, and conducting experimental measurement. The distributed resistance–inductance–capacitance–conductance (RLCG) parameters are calculated from electromagnetic theory and semiconductor physics. Wideband S-parameters of the fabricated devices are obtained using on-wafer measurement with deembedding technique, and then compared against 3-D full-wave simulations and analytical solutions, exhibiting good agreement up to 50 GHz. Results show that the proposed coaxial SIS TSV offers flexible impedance control, good matching, and low insertion loss, and supports 30-Gbps data transmission with the simpler structure as well as the lower fabrication cost compared with various coaxial TSV structures reported to date.

Copper Through Silicon Vias Studied by Photo-elastic Scanning Infrared Microscopy

The in-plane stress distribution in copper through silicon vias (TSV) ensembles of different design has been studied by the scanning infrared stress explorer (SIREX). SIREX is a reflection-based plane polarimeter particularly developed for the high-resolution stress state visualization in silicon-based electronic and mechanic devices. The SIREX method is based on the principle of stress-induced birefringence. We demonstrate that the silicon crystal matrix around the TSV is optically anisotropic with a stress distribution being similar to fields which are known from point-like stress sources. The maps of optical anisotropy have been converted into maps of difference of principal stress components Δσ with a resolution of a few kPa. We show that magnitude and direction of Δσ depend on the geometrical design of the TSV, in particular on length and diameter. The average radial profile of magnitude is discussed. In consequence, we offer a promising tool and method for the non-destructive evaluation of TSV structures in view of their stress characteristics and integrity.

Thermally-induced failures of copper through-silicon via structures evaluated by the strain energy density model

Based on the current density (CD) experimental results reported in a literature for the copper through-silicon vias (TSVs) arising in the Cu/Ti/SiO2/Si wafer structure, the CD solutions were obtained through simulations in the ANSYS/LS-DYNA software linked with the “Johnson-Cook (J-C) Constitutive Model” module in this study. The numerical schemes are developed to obtain the following contents: (1) the determinations of the unknown coefficients in the J-C model by conducting the microtensile tests for per each component of the TSV structure; (2) the earliest element failure caused by the thermal strain/stress; (3) the critical stress and time at potential failure location modeled by the J-C model; and (4) the evaluations of strain energy density (Wfailure) required for element failures in the components and the effect of heat generation rate in per unit volume of Cu film on element failure. The numerical solutions predicted by the present models are confirmed to be very close to the reported experimental results, and thus validate the present predictions for temperature and time and the sequence of elements with the earliest failure in their component. The strain energy density (Wfailure) required to start the failure of an element is found to be dependent upon the TSV component material only, and is independent of the element's location in the same component. The heat generation in the Cu film is of importance to the order of the TSV components reaching its Wfailure, the time to have Wfailure increases along with the distance of the TSV component from the lateral surface of the Cu film. The smaller the distance is, the earlier the time that the Wfailure of an element is reached. An appropriate combination of a Ti film with a large thickness and SiO2 film with a small thickness can reduce the maximum effective stress (σmax) and provide an efficient barrier for copper diffusion into the Si wafer substrate. This study can provide an efficient method for the design and failure protection of TSV structures.

A Measurement Method on Nanoscale Thickness of the Ti Barrier Layer of TSV Structure for 3-D IC

As the characteristic dimension of an integrated circuit (IC) continuously scales down, together with the requirements of low power consumption, multiple functionality, and cost effectiveness, the conventional IC transforms into a 3-D IC. Through-silicon via (TSV) is a promising and preferred way to realize the reliable interconnection for a 3-D IC. Thus, accurate measurement of the critical structural parameters plays an important role in securing the integrity and reliability of TSV. In this paper, a novel image-processing-based measurement method is proposed to measure the barrier layer thickness and step coverage of TSV. Since the thickness of the barrier layer is generally less than 100 nm, which is a drawback of the conventional SEM method, we used the material information from SEM as well as structural prior of TSV to infer the barrier layer thickness on nanoscale. In addition, we further achieved the step coverage of thin films in TSV using the proposed measurement method.