Through Silicon Via Diameter Research Articles

Investigation of heat transfer performance for through-silicon via embedded in micro pin fins in 3D integrated chips

Thermal management of 3D integrated chip (IC) with through silicon vias (TSV) is critical to achieving optimal overall system performance. In this work, the electrothermal coupling effect of TSV in micro pin fins embedded in a 3D IC was numerically investigated with deionized water as the coolant. The effects of various parameters, including the layouts of micro pin fin and TSV, TSV diameter, oxide thickness, and pin fin structures, on electrothermal coupling behaviors were analyzed. The results indicate that increasing TSV diameter, voltage loading of TSVs, and oxide thickness leads to higher temperature peaks and greater temperature differences between TSVs and pin fins. A C-shaped layout for the TSV and micro pin fins was found to facilitate heat transfer. And the best comprehensive heat transfer performance was achieved with an extended fin angle of 30 degrees for the micro pin fins. The findings contribute to the development of effective thermal management strategies for 3D ICs with TSVs, highlighting the importance of considering various parameters when designing micro pin fins and TSV layouts to optimize electrothermal coupling behaviors.

Thermal–Mechanical and Signal Reliability of a New Differentiated TSV

The thermal–mechanical and signal reliability of through-silicon via (TSV) occupies an important position in three-dimensional integrated circuits (3D-ICs). However, few studies combined the thermal–mechanical and signal reliability are found. In the work, a new differentiated structure of TSV is proposed to decrease the peak thermal stress without affecting signal integrity. The effect of TSV diameter on the peak thermal stress and its location is deeply investigated to decrease the stress. Compared with regular TSV, the differentiated TSV can reduce 22% peak thermal stress and 68% occupied silicon area. More differentiated TSVs can be placed in the same Si substrate by considering the influence of thermal stress between TSVs. Meanwhile, the differentiated TSV can better shield crosstalk noise with ensuring signal integrity.

Multiobjective Optimization for Heat Transfer Performance of Micro-Fins and Signal Integrity of Key Interconnect Technologies in 3-D Integrated Chips

This article is devoted to the synergistic design of the thermal management and signal integrity for 3-D integrated chips. The structure parameters of the micro-fin and interconnected components are optimized to obtain a balanced performance of chip heat dissipation and signal integrity. The 3-D integrated chip flows heat transfer model under the action of electrothermal coupling is developed. A full-wave electromagnetic simulation model of the signal interconnection components is proposed with the same structural parameters. The effects of various structural factors on the heat transfer performance and signal integrity of 3-D integrated chips are investigated. A multiobjective optimization algorithm is carried out to simultaneously reduce the total thermal resistance of the 3-D integrated chip and the signal transmission losses of the critical interconnect components. The results show that the total thermal resistance of the 3-D IC becomes lower with a larger through-silicon via (TSV) diameter, micro-fins height and micro-fin radius, and smaller oxide thickness. When the TSV diameter and oxide thickness increase, the height and radius of the micro-fins are reduced to facilitate the signal transmission of the chip’s interconnected components. The response surface analysis method was used to design the experimental combination and thus obtain the fit function for the performance of the two objectives. Hundred sets of Pareto optimal solutions are obtained by multiobjective optimization. The technique for order preference by similarity to ideal solution (TOPSIS) method is used to select the weights of the two optimization objectives to determine the optimal solution. When thermal resistance and signal transmission are given equal weight in the chip design, thermal resistance is reduced by 13.8%, and signal transmission efficiency is improved by 9.74%. The study has important implications for chip thermal management and signal integrity.

Heterogeneous 3-D Integration of Multitier Compute-in-Memory Accelerators: An Electrical-Thermal Co-Design

Emerging nonvolatile memory (eNVM)-based compute-in-memory (CIM) accelerators have been proven in silicon for machine learning at the macrolevel. To fully unleash the system-level benefits, the heterogeneous 3-D integration (H3D) using through-silicon via (TSV) is a promising approach, to: 1) address the challenges of area-hungry peripheries in CIM accelerators; 2) solve the 2-D scaling challenges of eNVM; and 3) stack enormous amount of embedded memories that are required in state-of-the-art deep neural network models. This article presents an electrical-thermal co-design of multitier CIM accelerators, based on SRAM and/or eNVM, with hybrid technology nodes for logic and memory tiers. We benchmark the CIM accelerators on 8-bit ResNet-34 for ImageNet recognition, with layer-by-layer and pipelined schemes, respectively. By sweeping TSV diameter from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$30~\mu \text{m}$ </tex-math></inline-formula> to 100 nm, we investigate the tradeoffs of system performance metrics (TOPS/W, TOPS, and TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and H3D challenges (thermal and IR-drop in power delivery). Finally, we find the sweet spot of TSV diameter for multitier H3D system is 1– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3~\mu \text{m}$ </tex-math></inline-formula> , to guarantee balanced area-overhead, performance, and IR-drop in power delivery. The extended benchmark framework is released on GitHub ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><uri>https://github.com/neurosim</uri></i> ) as an open-source tool for the research community.

Void-free Copper Electrodeposition in High Aspect Ratio, Full Wafer Thickness Through-Silicon Vias with Endpoint Detection

High density interconnects are required for increased input/output for microelectronics applications, incentivizing the development of Cu electrochemical deposition (ECD) processes for high aspect ratio through-silicon vias (TSVs). This work outlines Cu ECD processes for 62.5 μm diameter TSVs, etched into a 625 μm thick silicon substrate, a 10:1 aspect ratio. Cu ECD in high aspect ratio features relies on a delicate balance of electrolyte composition, solution replenishment, and applied voltage. Implementing a CuSO4-H2SO4 electrolyte, which contains suppressor and a low chloride concentration, allows for a tunable relationship between applied voltage and localized deposition in the vias. A stepped potential waveform was applied to move the Cu growth front from the bottom of the via to the top. Sample characterization was performed through mechanical cross-sections and X-ray computed tomography (CT) scans. The CT scans revealed small seam voids in the Cu electrodeposit, and process parameters were tuned accordingly to produce void-free Cu features. During the voltage-controlled experiments, measured current data showed a characteristic current minimum, which was identified as an endpoint detection method for Cu deposition in these vias. We believe this is the first report of this novel endpoint detection method for TSV filling.

Three-dimensional hybrid bonding integration challenges and solutions toward multi-wafer stacking

Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 µm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV) <2 µm to an ultimate thinning as low as 3 µm. Alignment performance was characterized by post-bonding for two superposed hybrid bonding interfaces. In our set of wafers, modeling the alignment with translation, rotation, and scaling components enables us to optimize the residuals down to 3σ < 100 nm. A process flow of thin TSV with a fine pitch of 2 µm for high-density vertical interconnect through a three-wafer stack was developed. Via-last TSV architecture was adopted with 1 µm TSV diameter and 10 µm thickness. Lithography, etching solutions, Ti/TiN barrier deposition, and void-free Cu filling solutions were demonstrated. TSV cross sections after CMP and connections with top and bottom Cu damascene lines show good profile control. Process developments are matured and can be reliably used in the fabrication of an electrical test vehicle including vertical interconnects associating multi-wafers stacking with a hybrid bonding process and high-density thin TSV applicable to low pitches (<5 µm).

Bottom-up Copper Electrodeposition in 20:1 Aspect Ratio, 20 Μm Pitch through Silicon Vias

Heterogeneous integration (HI) offers a path to increase bandwidth density and reducing power consumption per area for advanced microelectronic systems by minimizing fan-in/out structures and reducing parasitics. To achieve state-of-the-art areal bandwidth density, 3D HI is required with through silicon vias (TSVs) with extremely tight interconnect pitches (< 50 µm) and high aspect ratios. Fabrication and fill of these proposed TSVs pose significant challenges including substrate thinning, high aspect ratio deep reactive ion etching (DRIE), conformal thin film deposition to deposit insulating layers as well as seed metals for electrodeposition, and void-free fill of the TSVs. Here, we target an interconnect pitch of 20 µm and TSV diameter of 5 µm. At these dimensions, DRIE lag limits the TSV depth to 100 µm. The TSVs are integrated using a via-last scheme with atomic layer deposition (ALD) Al2O3 as the insulating liner and ALD Pt serving as both the barrier and electrochemical deposition (ECD) seed liner. In this work, we describe the integration scheme for these high density TSVs and focus on the ECD process for achieving a void-free fill with Cu as well as characterization approaches using focus ion beam (FIB) cross sectioning.Recent work on Cu ECD has demonstrated the efficacy of a two-additive acid sulfate electrolyte system based on a chemistry exhibiting a S-shaped negative differential resistance voltammogram1. The electrodeposition system presented is a 1.0 mol/L CuSO4 – 0.5 mol/L H2SO4 acid sulfate electrolyte containing a polyether surfactant and halide additive which promotes a bottom-up Cu growth profile via positive feedback between localized disruption of adsorbed polyether-halide layer and metal deposition. This electrolyte has been applied to potentiostatic filling of a variety of geometries with both micro-scale1 and mm-scale2 TSVs as well as current controlled bottom-up filling from a conformally conductive seed metal3. This system relies on fine tuning of applied bias, adsorbate concentrations, convection, and deposition time to ensure a bottom-up deposition regime is maintained in a particular via geometry.Previous work developed parameters for filling 600 µm deep 5:1 aspect ratio TSVs and the same parameters were applied to 600 µm deep 10:1 aspect ratio TSVs with drastically different filling results.2 In this work, we further adjust the relevant ECD parameters to fill 20:1 aspect ratio TSVs that are 100 µm deep.In fine pitch, high aspect ratio ECD, characterization of the deposited fill profile is important and is difficult to obtain using mechanical cross-sectioning. Here, we use a characterization approach which relies on focused ion beam (FIB) cross-sectioning rather physical grinding and polishing. The FIB mills into the surface of the sample at a 38º angle with respect to the surface of the sample while the electron beam collects a series of images looking down at the sample, as shown in Figure 1.The series of images collected throughout the FIB milling process are then reconstructed to generate a cross-sectional image. FIB cross-sectioning is also used to provide granular detail about deposition morphology and grain size of the ECD Cu that can be lost during mechanical cross-sectioning. Figure 2, shows a top down scanning electron microscopy image of the TSV sample after milling at 38º and the resulting reconstructed cross-sectional image. T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012).L. A. Menk, D. Josell, T. P. Moffat, E. Baca, M. G. Blain, A. Smith, J. Dominguez, J. McClain, P. D. Yeh, and A. E. Hollowell, Journal of the Electrochemical Society, 166 (1) D3066-D3071 (2019).L. A. Menk, E. Baca, M. G. Blain, J. McClain, J. Dominguez, A. Smith, and A. E. Hollowell, Journal of the Electrochemical Society, 166 (1) D3226-D3231 (2019) Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. This work was funded by the DARPA Photonics in the Package for Extreme Scalability (PIPES) program under award number HR001119S0004. The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. Figure 1

Hybrid Bonding of Via-middle TSV Wafer Fabricated using Direct Si/Cu Grinding, Residual Metal Removal, CVD, and CMP

Abstract We performed hybrid bonding of a via-middle through-silicon via (TSV) wafer that was fabricated using direct Si/Cu grinding, residual metal removal, chemical vapor deposition of a rear-side insulator, and chemical mechanical polishing. The rear side of the via-middle TSV wafer (wafer diameter: 197 mm, wafer thickness: 22 μm, TSV diameter: 5.5 μm, and total thickness variation: &amp;lt;2 μm), which was mounted on a support glass, was bonded to a Cu electrode wafer (wafer diameter: 200 mm, wafer thickness: 625 μm, and Cu electrode diameter: 6 μm). The bonding was performed at room temperature via a surface-activated bonding using a Si ultrathin film. After hybrid bonding, the support glass was debonded, and vacuum annealing was performed. Cross-sectional observations and electrical measurements of the bonded samples were also performed. Both the SiO2–SiO2 interface and the TSV-Cu electrode interface were bonded by the Si ultrathin film. The measured resistance of the TSV-Cu electrode pair was low (approximately 0.12 Ω), and the leakage current between the TSV-Cu electrode pairs was low (1 pA at 5 V).

Design Rules for TSV Membranes

The thermo-mechanical robustness of the bottom edge of an open through silicon via (TSV) is investigated by simulating the most critical step during the TSV process flow. In this step, stress arises due to the different thermal expansion coefficients of the materials forming the TSV. By employing the finite element method, the potential energy release rate of a crack at the TSV edge is calculated. The potential energy release rate, which quantifies the crack driving force, reaches its maximum when the diameter of the metal layers is ${\sim }1.25\times $ and ${\sim }1.5\times $ of the TSV diameter. Furthermore, when the metal diameter is three times the TSV, the crack driving force is reduced by ~50% for both aluminum and copper layers forming the TSV membrane. It was found that the crack tends to propagate perpendicularly to the TSV conductive layer, consistently with experimental observations. Meanwhile, the influence of the TSV membrane on the TSV conductive layer is negligible at distances further than 10% of the TSV height. Results show also that the reduction of 25% of the metal amount of the thickest layer lowers the crack driving force by 40% in comparison to the continuous layer.

Void-Free Copper Electrodeposition in Full Wafer Thickness through-Silicon Vias with 10:1 Aspect Ratios

The incorporation of copper-filled, mesoscale through-silicon-vias (TSVs) as a three-dimensional integration technique allows for increased input/output per unit volume compared to wire bonded microelectronic devices. Mesoscale TSVs that span the full thickness of a silicon wafer allow for preservation of a large radius of curvature during multi-layer device fabrication and for conservation of mass in the device, which is often a requirement in MEMS applications. The damascene process is commonly implemented for Cu electrodeposition in high aspect ratio features and typically involves a three-additive system in a CuSO4-H2SO4 electrolyte. However, a single-additive system has recently been shown capable of achieving bottom-up superfilling in features with higher aspect ratios than those commonly used in damascene interconnects.[i] This resistive electrodeposition system utilizes CuSO4, methane sulfonic acid (MSA), chloride, and a poloxamine suppressor additive. Cyclic voltammetry (CV) can be used to characterize the plating solution and identify a potential range that exhibits hysteresis in the voltage-current relationship that is caused by suppressor disruption at the cathode surface during electrodeposition. This hysteretic region serves as an operating window where void-free Cu filling of high aspect ratio features may be achieved. Using this chemistry, potentiostatic and galvanostatic plating conditions for void-free filling were developed for 100 μm diameter vias that are 600 μm deep, a 6:1 aspect ratio.[ii],[iii] Cu electrodeposition in TSVs with a higher aspect ratio of 10:1 is currently under investigation. These TSVs have a 62.5 μm diameter etched into a 625 μm thick silicon-on-insulator (SOI) wafer. Conditions that produce void free, bottom-up filling for 100 μm diameter TSVs have not directly translated to fill 62.5 μm diameter TSVs. In this work, the poloxamine suppressor concentration, current, potential, and sample rotation rate were varied to analyze their effect on the fill profile in these 62.5 μm diameter TSVs. Fill profiles were analyzed after mechanically cross-sectioning and optically imaging the samples. Cu fill profiles were also obtained through X-ray computed tomography (CT) scans. This work details the experimental approach associated with determining galvanostatic and potentiostatic plating conditions for 62.5 μm diameter TSVs and presents the resultant fill profiles of Cu in these vias. Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. [i]. Moffat, T. P., and D. Josell. "Extreme bottom-up superfilling of through-silicon-vias by damascene processing: suppressor disruption, positive feedback and turing patterns." Journal of the Electrochemical Society 159.4 (2012): D208-D216. [ii]. Menk, L. A. et. al. “Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology.” Journal of the Electrochemical Society 166.1 (2019): D3066-D3071. [iii]. Menk, L. A. et. al. “Galvanostatic Plating with a Single Additive Electrolyte for Bottom-Up Filling of Copper in Mesoscale TSVs” Journal of the Electrochemical Society 166.1 (2019).

Study on copper protrusion of through-silicon via in a 3-D integrated circuit

The through-silicon via (TSV) approach is crucial for three-dimensional integrated circuit (3-D IC) packaging technology. However, there are still several challenges in the TSV fabrication process. One of the widely known challenges is via protrusion phenomenon. Annealing a TSV wafer makes the copper (Cu) TSVs under high stress and may form a protrusion where the Cu is extruded out of the TSV structure. The phenomenon occurs because of the large mismatch in the coefficient of thermal expansion between Cu via and silicon (Si) layer. Cu protrusion is able to cause crack, delamination of the back-end-of-line and short circuit of the chip, thus, it is a dangerous threat to the metal layer interconnect. Experiments are conducted to characterize the protrusion using several techniques. Scanning electron microscope is used to observe the protrusion topography and measure the height. Electron backscatter diffraction (EBSD) technique is implemented to study the grain size distribution, local texture and microstructure evolution inside Cu vias. For the experiment, arrays of 10 μm diameter TSVs are fabricated and annealed in argon gas environment in six different temperatures. In this paper, finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions. Correlation between numerical results and experimental data is then performed. Based on the verified FEA methodology, several parametric studies are then conducted, including the effects of annealing temperature on Cu protrusion, residual stress distributions of TSV structures. The simulation results are helpful to understand and solve the key problem in TSV fabrication process and reliability challenge.

Study of Annular Copper-Filled TSVs of Sensor and Interposer Chips for 3-D Integration

Actually, the 3-D integrating process is often viewed as the integration of wafer thinning, through-silicon vias (TSVs) etching and filling, redistribution layer formulation, and microbump bonding. The TSV formulation is a critical process because TSV decides the quality of the interconnection. In this paper, the annular copper-filled TSVs are fabricated into the sensor and interposer chips, which are thinned to 100 $\mu \text{m}$ , and 10- $\mu \text{m}$ -diameter TSV is etched and annularly filled by 2- $\mu \text{m}$ -thick copper only utilizing sputtering. It can significantly simplify the chip fabricating process, which only includes the TSV etching (deep reactive-ion etching), insulating layer formation, barrier layer sputtering and copper layer sputtering, and peeling. The thermal reliability of the annularly filled TSV structure is studied by the finite-element simulation, and it is found that the thermal stress is markedly reduced, and in the thermal cycle test, annularly filled TSV samples show better reliability. Meanwhile, the measured electrical conductivity shows a slightly worse but enough electrical conductivity property.

Mechanisms of copper protrusion in through-silicon-via structures at the nanoscale

Thermal stress-induced copper protrusion is frequently observed in through-silicon-vias (TSVs) based three-dimensional system integration. In this study, the detailed process of Cu protrusion is reproduced on the atomic scale using a two-mode phase-field-crystal (PFC) model, and the mechanisms of protrusion are identified. To simulate thermal loading, a “penalty term” is added to the governing equation of the PFC model. The application of loading on the TSVs induces copper grain deformation and grain boundary (GB) migration at the nanoscale. Furthermore, the simulation results suggest that the Cu protrusion is resulted from diffusional creep, involving both Nabarro–Herring creep and Coble creep. The obtained power index of diffusional creep p is around 2.16, suggesting that lattice diffusion contributes more to protrusion than GB diffusion does. The protrusion height in micron-scale TSVs predicted by extrapolating the relationship between the protrusion height and diameter of nanoscale TSVs agrees with the experimental data.

High-Resolution E-Jet Enhanced MEMS Packaging

High-resolution electrohydrodynamic inkjet printing has potential to simplify the existing MEMS package fabrication through its additive and digital properties without sacrifices in the I/O density of the package. Initially, the replacement of certain lithographic process steps would lead to decreased material consumption and increased cost-effectiveness of the package fabrication; in long term, the large-scale adoption of additive process steps would enable increasing device customizability and lead to cost-effective fabrication of small batches and even fully tailored device specific MEMS packages. In our work, we have demonstrated the feasibility of this approach by replacing selected lithographic process steps by using high-resolution inkjet technology (Super Inkjet, SIJ Tech.) for metallization of high-density redistribution layers (RDL), metallization of through-silicon-vias (TSV) and fabrication of under bump metallization (UBM). Fully printed high-density redistribution layer (RDL) A fully printed high density RDL in two metallization layers was demonstrated with a combination of Super Inkjet (SIJ) and conventional inkjet printing (DMP-2831). The SIJ was used for the metallization of 5/5 µm W/S high-density circuitry in MET1 and MET2 and DMP for the dielectric layer separating the metallization layers. In order to achieve low resistance conductors with minimal footprint, multilayer printing was employed resulting in a high aspect ratio of over one. The MET1 to MET2 microvia was also additively fabricated by first printing a narrow ~10µm pillar in MET1 with SIJ, then surrounding the pillar with DMP printed dielectric layer and finally connecting the top of the pillar with SIJ printed MET2 conductors. [1] A fully printed RDL increases the customizability of the package fabrication process to a level where each individual interposer on wafer could be fitted with customized RDL to accommodate a specific MEMS device. In addition, the material consumption is reduced significantly since the fully printed RDL does away with global deposition of metal, masking and etching required in standard lithography based metallization. It is also important to notice that these advantages are achieved without sacrificing the density the RDL: the 5/5µm width and spacing for conductors and 10µm microvia diameter are similar to what is achieved with current lithographic processes. Additive metallization of high-density through-silicon-vias (TSV) The sub-femtoliter droplet size of the SIJ and concomitant fast evaporation rate was utilized in rapid metallization of high-density TSVs with top diameter of 23µm and spacing of 10µm. In standard practice CVD, PVD, electroplating or electroless deposition are utilized for metallization of high density TSVs leading to long process time and low level of customizability. The conventional inkjet printing could be used for over 50µm TSV diameters, but it is difficult to achieve stable operation with a 1pl cartridge which could produce small diameter droplets for filling the high density TSVs of 20µm diameter; also the low evaporation rate of the relatively large droplets would prolong the process time since evaporation step would need to be included in the process; in addition, the positioning accuracy of the conventional inkjet printer (e.g. DMP) might not be sufficient for this application. In this regard it was noticed that the SIJ printing has many advantages: first, the sub-femtoliter droplet size leads to fast evaporation rate enabling the metallization of the vias at room temperature without substrate heating or evaporation steps; second, the positioning accuracy of the SIJ stage is under 1µm enabling accurate deposition of the ink in to the TSV; third, since most of the solvent in the droplets is already evaporated during the flight, the chances for creating gas pockets in the filling are reduced. [2] High-resolution inkjet printing for creating smooth UBM The previously discussed approaches for utilizing the high-resolution Super Inkjet printing were restricted to features inside the interposer. However, this fabrication technology also finds utility on the outside of the package, which does not necessarily need such high-density features, but where low surface roughness is important. Highlighting this advantage, a smooth under bump metallization has been fabricated with SIJ on top of a large diameter partially metallized TSV; the TSV has been filled with SIJ printed polymer dielectric. [3] References Laurila et al, “Combination of E-jet and inkjet printing in additive fabrication of multilayer high-density RDL of silicon interposer”, IEEE Trans. Electr. Dev., vol. 64, no. 3, pp. 1217-1224, March 2017 Khorramdel et al, “Metallization of high-density TSVs using Super Inkjet technology”, 2015 IEEE 65th ECTC conf., San Diego, 2015, pp. 41-45 Khorramdel et al, “Inkjet printing technology for increasing the I/O density of 3D TSV interposers”, Microsystems & Nanoengineering, vol. 3, 17002, Apr. 2017

Development of a Four-Side Buttable X-Ray Detection Module With Low Dead Area Using the UFXC32k Chips With TSVs

Nowadays, single photon counting pixel hybrid detectors are becoming increasingly popular in high-energy physics, X-ray detectors for synchrotron applications, and medical imaging. Readout chips for these detectors usually have the area of a few square centimeters and are designed to be abutted on three sides. However, many applications require large-area detectors without dead areas. The through-silicon vias (TSVs) aim to minimize the dead area and in that way to enable development of four-side buttable large-area detectors. AGH, Krakow, and IZM, Berlin, have undertaken a common effort to apply TSV (via last) technology to the readout integrated circuit called UFXC32k containing a matrix of $128 \times 256$ pixels, with a pixel pitch of $75~\mu \text{m}$ and a total area of 2 cm2. The TSVs were applied to the 87 I/O pads located at the bottom of UFXC32k IC. A TSV diameter of $20~\mu \text{m}$ was chosen while the wafers were thinned to $100~\mu \text{m}$ . The redistribution layer and the array of pads for solder bumping were distributed at the bottom side of the chips. Two UFXC32k chips with TSVs were attached to a single, 320- $\mu \text{m}$ -thick silicon sensor and finally, the chip detector modules were attached to low-temperature co-fired ceramic boards. The $2 \times 2$ cm2 plug-in detector modules were successfully built and tested.

Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions and wet cleaning was performed using an organic alkaline solution to remove reaction products generated by the etchback step on the first metal layer. By this process, a number of small TSVs (TSV diameter: 6 µm; TSV depth: 22 µm; number of TSVs: 20,000/chip) could be formed uniformly on an 8-in. wafer. The electrical characteristics of small TSVs formed by this via-last TSV process were investigated. The TSV resistance determined by four-terminal measurements was approximately 24 mΩ. The leakage current between the TSV and the Si substrate was 2.5 pA at 5 V. The TSV capacitance determined using an inductance–capacitance–resistance (LCR) meter was 54 fF, while the TSV yield determined from TSV chain measurements was high (83%) over an 8-in. wafer.

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.

Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis

Through silicon via (TSV)-based 3-D integrated circuit has introduced the solution to limitlessly growing demand on high system bandwidth, low power consumption, and small form factor of electronic devices. As the system design aims for higher performance, the physical dimensions of the channels are continuously decreasing. With TSV diameter of less than 10 $\mu \text{m}$ and pitch of several tens of micrometers, the I/O count has increased up to the order of tens of thousands for wide bandwidth data transmission. However, without highly precise fabrication process, such small structures are susceptible to a variety of defects. For the first time, in this paper, we propose a noninvasive defect analysis method for high-speed TSV channel. With designed and fabricated test vehicles, the proposed method is demonstrated with ${S}$ -parameter and time-domain reflectometry measurement results. In addition, we present equivalent circuit models of TSV daisy-chain structures, including the circuit components for open defect and short defect. With characterized dominant factors in each frequency range, $S_{11}$ is analyzed to distinguish and locate the defects by the amount of capacitance, resistance, and inductance that the signal experiences. ${S}$ -parameter measurement sufficiently allows high-frequency defect analysis of TSV channel without destroying the test sample. We experimentally verified the accuracy of the suggested model by comparing the ${S}$ -parameter results from circuit simulations and measurements. Finally, the model is modified to discuss the effects of open defect and short defect on the electrical characteristics of TSV channel.

Risk assessment of the crack propagation and delamination of the Cu-to-Cu direct bonded (CuDB) interface

Through Silicon Via (TSV) technology with micro joint has been identified as the 3D package technology to overcome the limitations of I/O density and enhances the system performance compared to that of the conventional flip chip packages. One of the challenges of the reliable 3D TSV packages is stacking and joining of thin wafers or dies. The conventional micro joining methods, such as use of solder bumps, cause many reliability problems, such as intermetallic compound (IMC) formation, electromigration, delamination, creep, and fatigue problems. As an alternative, copper-to-copper direct bonding (CuDB) has been proposed. CuDB enables reduction in fabrication process steps, can obtain higher interconnect density and enhanced thermal conductivity. However, the CuDB interface has potential reliability risk since the bonding is typically performed by compression at high temperature. Several prior studies have reported formation of small voids between the bonding interfaces of the CuDB that can lead to crack initiation, propagation and thereby delamination of the entire interface. The defect can result in failure of the entire package during its fabrication process or operation.This study is risk assessment of possibility of crack propagation at the CuDB interface using fracture mechanics approach. Finite element (FE) analysis and design of experiments (DOE) are used. A crack is assigned at the interface of the CuDB to mimic a small void. Initial crack location and dimensional variables (Initial crack length, Cu pad diameter and pitch, and TSV diameter and pitch) are varied to quantify the risk. The strain energy release rate (SERR) around the crack tip is calculated and compared with the critical SERR, obtained by experiments, to judge the possibility of crack propagation. Sensitivity analysis of design parameters is conducted. As a result, this study provides design recommendations that can minimize interfacial failure of the CuDB. In addition, this study explores various numerical modeling methodologies that can be implemented for efficient failure prediction of the interfaces.

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias

This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking $\mu {\rm P}$ and high density cache memory, with $> 2~{\rm GHz}$ operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50 $\mu{\rm m}$ pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1 $\mu{\rm m}$ . The paper concludes with comments on the challenges for future 3D DRAMs.